DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown, or the feature(s) canceled from the claim(s):
the second gate electrode layer is in contact with the third dielectric feature and one surface of the second semiconductor layer as recited in claim 7,
the first gate electrode layer is in contact with the second dielectric feature and one surface of each of the first and third semiconductor layers as recited in claim 11, and
the second gate electrode layer is in contact with the third dielectric feature and one surface of each of the second and fourth semiconductor layers as recited in claim 17
No new matter should be entered. The specification defines the gate electrode layers as elements 182 and 184, the dielectric features as elements 130, 134 and 136, and the semiconductor layers as elements 106. The drawings fail to show either of 182 or 184 contacting any of 130, 134, 136 or 106.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-8, 11 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 7 recites “the second gate electrode layer is in contact with the third dielectric feature and one surface of the second semiconductor layer.” in lines 1-2.
¶ 0042 of the instant specification discloses a third dielectric layer 136, and ¶ 0076 discloses gate electrode layers 182 and 184, and semiconductor layer 106. Fig. 29 among others discloses 182 and 184 surrounding 106 in at least regions 112a and 112b. However, 182 and 184 are prevented from contacting either of 136 or 106 by intervening dielectric layers 178 and 180. Accordingly, claim 7 fails to comply with the requirements of 35 USC 112(a), as the claimed features of “the second gate electrode layer is in contact with the third dielectric feature and one surface of the second semiconductor layer” were not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
For the purpose of compact prosecution, the Examiner has interpreted claim 7 as follows:
7. The semiconductor device structure of claim 6, wherein the second gate electrode layer surrounds the third dielectric feature and one surface of the second semiconductor layer.
Claim 8 is rejected under 35 USC § 112(a) for implicitly including the subject matter above.
Claim 11 recites “wherein the first gate electrode layer is in contact with the second dielectric feature and one surface of each of the first and third semiconductor layers” in lines 1-2.
Fig. 21 discloses first gate electrode layer 182/184 separated from second dielectric feature 134, and separated from first and third semiconductor layers 106 in region 112b, by intervening high-k dielectric layer 180. Therefor, the application as originally filed fails to provide support for the features of claim 11.
For the purpose of compact prosecution, the Examiner has interpreted claim 11 as follows:
11. The semiconductor device structure of claim 10, wherein the first gate electrode layer surrounds the second dielectric feature and one surface of each of the first and third semiconductor layers.
Claim 17 recites “…wherein the second gate electrode layer is in contact with the third dielectric feature and one surface of each of the second and fourth semiconductor layers” in lines 1-3.
Fig. 21 discloses second gate electrode layer 184 separated from third dielectric feature 136, and separated from second and fourth semiconductor layers 106 in region 112c, by intervening high-k dielectric layer 180. Therefore, the application as originally filed fails to provide support for the features of claim 17.
For the purpose of compact prosecution, the Examiner has interpreted claim 17 as follows:
17. The semiconductor device structure of claim 15, wherein the second gate electrode layer surrounds the third dielectric feature and one surface of each of the second and fourth semiconductor layers” in lines 1-3.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “the first dielectric feature” in lines 3-4, which lacks proper antecedent basis.
For the purpose of compact prosecution, the Examiner has interpreted claim 18 as follows:
18. A semiconductor device structure, comprising:
a dielectric feature disposed over an insulating material;
a first plurality of semiconductor layers extending laterally from a first side of the
a second plurality of semiconductor layers extending laterally from a second side of the
Claim 20 recites “a third gate electrode layer disposed over the dielectric feature, the first, and the second plurality of semiconductor layers, the third gate electrode layer comprising a material chemically different from the first and second gate electrode layers” in lines 2-4 (emphasis added).
The meaning of the limitation “the first” is unclear, as parent claim 18 includes a first plurality of semiconductor layers, a first dielectric feature, and a first gate electrode layer. Therefore, the scope of claim 20 is indefinite.
For the purpose of compact prosecution, the Examiner has interpreted claim 20 as follows:
20. The semiconductor device structure of claim 19, further comprising:
a third gate electrode layer disposed over the dielectric feature, the first plurality of semiconductor layers, and the second plurality of semiconductor layers, the third gate electrode layer comprising a material chemically different from the first and second gate electrode layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni Litta et al. (PG Pub. No. US 2021/0193821 A1, hereinafter ‘Dentoni’) in view of Ando et al. (PG Pub. No. US 2020/0006356 A1).
Regarding claim 1, Dentoni teaches a semiconductor device structure (¶ 0050 & figs. 1, 8a: 100), comprising:
a first dielectric feature (¶ 0054: 104) extending along a first direction, (fig. 1: 104 extends in vertical direction) the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall (fig. 8a: left/right sidewalls of 104);
a first semiconductor layer (¶ 0056: 102a) disposed adjacent the first sidewall (fig. 8a: 102a disposed adjacent first sidewall of 104), the first semiconductor layer extending along a second direction perpendicular to the first direction (fig. 1: 102a extends along horizontal direction);
a second dielectric feature (¶ 0053: 108) extending along the first direction (fig. 1: 108 extends along vertical direction), the second dielectric feature disposed adjacent the first semiconductor layer (figs. 1, 8a: 108 disposed adjacent to 102a); and
a first gate electrode layer (¶ 0056: 114a) surrounding at least three surfaces of the first semiconductor layer (¶¶ 0089, 0095 & figs. 1, 8a: in region 10a, gate 114a wraps around and surrounds three surfaces of nanosheets 102a).
Dentoni does not teach a portion of the first gate electrode layer is exposed to a first air gap.
Ando teaches a semiconductor device structure (fig. 13 among others) including a portion of a first gate electrode layer (¶¶ 0051, 0056: 834/1302 and/or 874/1302, similar to 114a of Dentoni) is exposed to a first air gap (¶ 0049 & fig. 13: 834/1302 exposed to air gap 836A, 874/1302 exposed to air gap 876A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to expose the first gate electrode of Dentoni to an air gap, as a means to minimize threshold voltage variation (Ando, ¶ 0057).
Regarding claim 2, Dentoni in view of Ando teaches the semiconductor device structure of claim 1, further comprising:
a second semiconductor layer (Dentoni, ¶ 0052: 102c) disposed adjacent the second sidewall of the first dielectric feature (Dentoni, fig. 8a among others: 102c disposed on second sidewall of 104), the second semiconductor layer extending along the second direction (Dentoni, fig. 1: 102c extends along horizontal direction).
Regarding claim 3, Dentoni in view of Ando teaches the semiconductor device structure of claim 2, including a second dielectric feature (Dentoni, 108), a first semiconductor layer (Dentoni, 102a), and a first gate electrode layer (Dentoni, 114a). Dentoni in view of Ando teaches the first gate electrode layer disposed on the second dielectric feature and surrounding at least three surfaces of the first semiconductor layer (Dentoni, ¶ 0095 & figs. 1, 8a: 114a disposed in region 10a disposed on 108 and surrounds at least three surfaces of 102a).
Dentoni in view of Ando as applied to claim 2 above does not teach the semiconductor device structure further comprising:
a high-K dielectric layer disposed on the second dielectric feature and surrounding at least three surfaces of the first semiconductor layer, wherein the high-K dielectric layer is in contact with the first gate electrode layer.
However, Ando teaches a high-K dielectric layer (¶ 0050: 732) surrounding at least three surfaces of a first semiconductor layer (¶ 0035 & fig. 13: 732 disposed on at least three sides of semiconductor channels 114/116/118), wherein the high-K dielectric layer is in contact with the first gate electrode layer (fig. 13: 732 in contact with gate electrode portion 834 and/or 874).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device structure Dentoni in view of Ando with a high-k dielectric layer, as a means to provide a gate dielectric material with a thickness suitable for optimizing threshold voltage and improving electrical performance (Ando, ¶ 0022).
Furthermore, the combination of the high-k gate dielectric of Ando in the gate region of Dentoni would include the feature of a high-K dielectric layer (Ando, 732 or 772) disposed on a side surface of a second dielectric feature (Dentoni, 108).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Ando as applied to claim 3 above, and further in view of Miura et al. (PG Pub. No. US 2021/0082766 A1).
Regarding claim 4, Dentoni in view of Ando teaches the semiconductor device structure of claim 3, further comprising:
a second gate electrode layer (Dentoni, ¶ 0056: 114c) surrounding at least three surfaces of the second semiconductor layer (figs, 1, 8a: in region 30a, 114c formed to surround three surfaces of 112c).
Dentoni in view of Ando does not teach wherein the second gate electrode layer and the first gate electrode layer are chemically different from each other.
Miura teaches a semiconductor device structure (fig. 6E among others) including a second gate electrode layer (¶¶ 0089-0090: p-region gate structure including metal film 22) surrounding at least three surfaces of a second semiconductor layer (fig. 6E: 22 surrounds at least three surfaces of outer semiconductor layer 4) and a first gate electrode layer (¶¶ 0088, 0090: n-region gate structure including metal film 27) surrounding at least three surfaces of a first semiconductor layer (fig. 6E: 27 surrounds at least three surfaces of inner semiconductor layer 4),
wherein the second gate electrode layer and the first gate electrode layer are chemically different from each other (¶¶ 0087-0088: 22 and 27 are chemically different materials).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second gate electrode layer and the first gate electrode layer of Dentoni in view of Ano with chemically different materials, as a means to independently control required values of threshold voltages of separate FET devices (Miura, ¶ 0004).
Regarding claim 5, Dentoni in view of Ando and Miura teaches the semiconductor device structure of claim 4, comprising a second gate electrode layer (Dentoni, 114c).
Dentoni in view of Ando and Miura as applied to claim 4 above does not teach wherein a portion of the second gate electrode layer is exposed to a second air gap.
However, Ando teaches a second gate electrode layer (¶¶ 0051, 0056: 874/1302) is exposed to a second air gap (fig. 13: 874/1302 exposed to air gap 876A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to expose the second gate electrode layer of Dentoni in view of Ando and Miura to a second air gap, as a means to as a means to minimize threshold voltage variation in a second device region (Ando, ¶ 0057).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Ando and Miura as applied to claim 4 above, and further in view of Shiliang et al. (PG Pub. No. US 2022/0102520 A1).
Regarding claim 6, Dentoni in view of Ando and Miura teaches the semiconductor device structure of claim 4, comprising a second semiconductor layer (Dentoni, 102c) and a high-K dielectric layer (Ando, 732/772).
Dentoni in view of Ando and Miura does not teach the semiconductor device structure further comprising:
a third dielectric feature disposed adjacent the second semiconductor layer and extending along the first direction, wherein the high-K dielectric layer is disposed over the third dielectric feature.
Shiliang teaches a semiconductor device structure (fig. 25 among others) including first and second dielectric features (¶ 0149: 212), and a third dielectric feature (¶ 0170: 211) disposed adjacent a second semiconductor layer (¶ 0169 & fig. 25: 211 disposed adjacent to semiconductor channels 2012) and extending along a first direction (lateral direction of fig. 9), wherein a high-K dielectric layer (¶ 0131 high-k dielectric of gate structure 121) is disposed over the third dielectric feature (fig. 25: high-k gate dielectric of gate structure 121 disposed over side surfaces of 211).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device structure of Dentoni in view of Ando and Miura with the third dielectric feature of Shiliang, as a means to provide an isolation structure suitable to prevent bridging the first and second semiconductor layers, improving the electrical performance of the semiconductor structure (Shiliang, ¶ 0171).
Regarding claim 7, Dentoni in view of Ando, Miura and Shiliang teaches the semiconductor device structure of claim 6, wherein the second gate electrode layer surrounds the third dielectric feature and one surface of the second semiconductor structure (Miura, at least portion 27 of p-region gate structure surrounds dielectric feature 7, as modified to include 211 of Shiliang, and at least one surface of semiconductor structure 4).
Regarding claim 8, Dentoni in view of Ando, Miura and Shiliang teaches the semiconductor device structure of claim 7, wherein the second gate electrode layer is in contact with a portion of the high-K dielectric layer and a portion of the first gate electrode layer (Miura, fig. 6E: 22 of gate structure in p-region is in contact with high-k dielectric 21 and a portion of 27 of gate structure in n-region).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Rodder et al. (PG Pub. No. US 2015/0364546 A1).
Regarding claim 9, Dentoni teaches a semiconductor device structure (fig. 8a), comprising:
a first dielectric feature (¶ 0054: 104) having a first sidewall and a second sidewall opposing the first sidewall (fig. 8a: first and second sides of 104);
a first semiconductor layer (¶ 0052: 102a-bottom) extending laterally from the first sidewall (fig. 8a: 102a-bottom extending from right sidewall of 104);
a second semiconductor layer (¶ 0052: 102c-bottom) extending laterally from the second sidewall (fig. 8a: 102c-bottom extends away from left sidewall of 104);
a third semiconductor layer (¶ 0052: 102a-top) extending laterally from the first sidewall (fig. 8a: 102a-top extending from right sidewall of 104), the third semiconductor layer being parallel to and spaced apart from the first semiconductor layer by a first spacing (fig. 8a: 102a-bottom and 102a-top arranged in parallel and vertically spaced);
a fourth semiconductor layer (¶ 0052: 102c-top) extending laterally from the second sidewall and being parallel to the second semiconductor layer (fig. 8a: 102c-top extends from left sidewall of 104);
a first gate electrode layer (¶ 0056: 114a) surrounding at least three surfaces of each of the first and third semiconductor layers (¶ 0095 & figs. 1, 8a: 114a surrounds at least three surfaces of each of 102a-bottom and 102a-top); and
a second dielectric feature (¶ 0053: 108) disposed adjacent to the first and third semiconductor layers (fig. 8a: 108 arranged adjacent to 102a-bottom and 102a-top), the second dielectric feature being spaced apart from the first and third semiconductor layers by a second spacing (fig. 8a: horizontal spacing between 108 and 102a-bottom/top).
Dentoni is silent to wherein the second spacing is smaller than the first spacing.
Rodder teaches a semiconductor device (fig. 2C) including a third semiconductor layer being parallel to and spaced apart from a first semiconductor layer by a first spacing (fig. 3: nanosheets 310 spaced apart by distance ‘V’ and/or distance ‘H’), the first spacing being a results-effective variable (¶ 0045).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the first and/or second spacing of Dentoni, as a means to enable a larger effective conduction channel width per layout area (Rodder, ¶ 0052).
Furthermore, adjusting the first spacing of Dentoni sufficient to meet the claimed feature “the second spacing is smaller than the first spacing” would be a matter of routine optimization, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, Dentoni teaches the general conditions of a second dielectric feature being spaced apart from first and third semiconductor layers by a second spacing, Dentoni and Rodder both teach a first spacing between parallel first and third semiconductor layers, and Rodder teaches varying distances between parallel first and third semiconductor layers.
Regarding claim 10, Dentoni in view of Rodder teaches the semiconductor device structure of claim 9, further comprising:
a second gate electrode layer (Dentoni, ¶ 0056: 114c) surrounding at least three surfaces of each of the second and fourth semiconductor layer (Dentoni, ¶ 0094 & figs. 1, 8a: 114c surrounding at least three surfaces of each 112c).
Regarding claim 11, Dentoni in view of Rodder teaches the semiconductor device structure of claim 10, wherein the first gate electrode layer surrounds the second dielectric feature and one surface of each of the first and third semiconductor layers (Dentoni, figs. 1, 8a: 114a at least partially surrounds 108 and at least one surface of each 102a).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Rodder as applied to claim 10 above, and further in view of Ando.
Regarding claim 12, Dentoni in view of Rodder teaches the semiconductor device structure of claim 10, comprising first and second gate electrode layers (Dentoni, 114a and 114c).
Dentoni in view of Rodder does not teach wherein the first gate electrode layer is exposed to a first air gap, and the second gate electrode layer is exposed to a second air gap.
Ando teaches a semiconductor device structure (fig. 13 among others) including portions of first and second gate electrode layers (¶¶ 0051, 0056: 834/1302 and 874/1302, similar to 114a/114c of Dentoni) is exposed to respective first and second air gaps (¶ 0049 & fig. 13: 834/1302 exposed to air gap 836A, 874/1302 exposed to air gap 876A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to expose the gate electrodes of Dentoni to air gaps, as a means to minimize threshold voltage variation (Ando, ¶ 0057).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Rodder as applied to claim 10 above, and further in view of Miura.
Regarding claim 13, Dentoni in view of Rodder teaches the semiconductor device structure of claim 10, comprising a second gate electrode layer (Dentoni, 114c).
Dentoni in view of Rodder does not teach the semiconductor device structure further comprising:
a metal layer in contact with the second gate electrode layer.
Miura teaches a semiconductor device structure (fig. 6E) including a second gate electrode layer (¶ 0090: 22 and/or 27), and a metal layer (¶ 0089: 28) in contact with the second gate electrode layer (fig. 6E: 28 in electrical and/or physical contact with 22 and/or 27).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device structure of Dentoni in view of Rodder with a metal layer in contact with the second gate electrode layer, as a means to work function control and low resistance gate (Miura, ¶ 0090), optimizing threshold voltage and corresponding electrical performance of the semiconductor device structure.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni in view of Rodder as applied to claim 10 above, and further in view of Shiliang.
Regarding claim 14, Dentoni in view of Rodder teaches the semiconductor device structure of claim 10, comprising second and fourth semiconductor layers (Dentoni, 112c).
Dentoni in view of Rodder does not teach the semiconductor device structure further comprising:
a third dielectric feature disposed adjacent to the second and fourth semiconductor layers, the third dielectric feature being spaced apart from the second and fourth semiconductor layers by a third spacing smaller than the first spacing.
Shiliang teaches a semiconductor device structure (fig. 25 among others) including first and second dielectric features (¶ 0149: 212), and a third dielectric feature (¶ 0170: 211) disposed adjacent a second semiconductor layer (¶ 0169 & fig. 25: 211 disposed adjacent to semiconductor channels 2012) and extending along a first direction (lateral direction of fig. 9), wherein a high-K dielectric layer (¶ 0131 high-k dielectric of gate structure 121) is disposed over the third dielectric feature (fig. 25: high-k gate dielectric of gate structure 121 disposed over side surfaces of 211).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device structure of Dentoni in view of Rodder with the third dielectric feature of Shiliang, as a means to provide an isolation structure suitable to prevent bridging the first and second semiconductor layers, improving the electrical performance of the semiconductor structure (Shiliang, ¶ 0171).
Furthermore, adjusting the first and/or third spacing to meet the claimed feature of “a third spacing smaller than the first spacing” would be a matter of routine optimization, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, Dentoni teaches the general conditions of a second dielectric feature being spaced apart from first and third semiconductor layers by a second spacing, Dentoni and Shiliang both teach a first spacing between parallel first and third semiconductor layers, and Rodder teaches varying distances between parallel first and third semiconductor layers.
Regarding claim 15, Dentoni in view of Rodder and Shiliang teaches the semiconductor device structure of claim 14, further comprising:
a high-K dielectric layer (Shiliang, ¶ 0131) disposed on the first, second, and third dielectric features (Dentoni, figs. 1 & 8a, Shiliang, fig. 25: gate 114a/b/c of Dentoni and gate 221 of Shiliang, comprising the high-k dielectric of Shiliang, at least indirectly disposed on 104 and 108 of Dentoni and 211 of Shiliang), and the high-K dielectric layer surrounds at least three surfaces of each of the first, second, third, and fourth semiconductor layers (Dentoni, figs. 1 and 8a: gates 114a/114c, including the high-k material of Shiliang, surround at least three surfaces of each of 102a and 102c).
Regarding claim 16, Dentoni in view of Rodder and Shiliang teaches the semiconductor device structure of claim 15, wherein the high-K dielectric layer is in contact with a portion of the first gate electrode layer and a portion of the second gate electrode layer (Dentoni, figs. 1 & 8a: high-k dielectric material of Shiliang is gate dielectric which contacts gate electrodes 114a and 114c).
Regarding claim 17, Dentoni in view of Rodder and Shiliang teaches the semiconductor device structure of claim 15, wherein the second gate electrode layer (Dentoni, 114c, and/or right portion of 221 of Shiliang) surrounds (see 35 USC § 112(a) rejection above) the third dielectric feature and one surface of each of the second and fourth semiconductor layers (Shiliang, fig. 25: right portion of 221 surrounds a portion of 211 and plurality of channel layers 2012).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of Ando.
Regarding claim 18, Miura teaches a semiconductor device structure, comprising:
a dielectric feature (7) disposed over an insulating material (2);
a first plurality of semiconductor layers (4-left) extending laterally from a first side of the
a second plurality of semiconductor layers (4-right) extending laterally from a second side of the
a first gate electrode layer (n-WFM) surrounding each of the first plurality of semiconductor layers (fig. 6E); and
a second gate electrode layer (p-WFM) surrounding each of the second plurality of semiconductor layers (fig. 6E), wherein the first and second gate electrode layers comprises a material chemically different from each other (¶¶ 0096, 0098: n-WFM and p-WFM comprise different materials).
wherein the first gate electrode layer defines a gap between two neighboring semiconductor layers of the first plurality of semiconductor layers (fig. 8a: vertical gap between adjacent 102a).
Miura does not teach the gap comprises air.
Ando teaches a semiconductor device structure (fig. 13 among others) including a portion of a first gate electrode layer (¶¶ 0051, 0056: 834/1302 and/or 874/1302, similar to 114a of Dentoni) defining an air gap (¶ 0049 & fig. 13: 834/1302 defines air gap 836A, 874/1302 defines air gap 876A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first gate electrode of Dentoni to define air gap, as a means to minimize threshold voltage variation (Ando, ¶ 0057).
Regarding claim 19, Miura in view of Ando teaches the semiconductor device structure of claim 18, wherein the second gate electrode layer defines an air gap between two neighboring semiconductor layers of the second plurality of semiconductor layers (Miura, fig. 8a: gap between 102c, as modified to include air gap 836 A or 876A of Ando).
Regarding claim 20, Miura in view of Ando teaches the semiconductor device structure of claim 19, further comprising:
a third gate electrode layer (Miura, ¶ 0089: 28) disposed over the dielectric feature, the first plurality of semiconductor layers, and the second plurality of semiconductor layers (Miura, fig. 6E: portions of 28 disposed over 7, 4-left and 4-right), the third gate electrode layer comprising a material chemically different from the first and second gate electrode layers (Miura, ¶¶ 0068, 0088-0089: 28 chemically different than 22 and 27).
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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