Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “laterally” should be “lateral.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1-6 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20080191297 to Yang et al. (Yang).
Regarding Claim 1, Yang teaches in Fig. 2 at least, a semiconductor package, comprising:
a substrate 2 comprising a first conductive through-via 6;
a sensor die 16 disposed on the substrate;
a second conductive through-via 22 disposed on the substrate and electrically connected to the first conductive through-via;
an insulating encapsulant 18 laterally encapsulating the sensor die and the second through-via;
a first redistribution structure 24 disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via;
and a second redistribution structure 8/10 disposed on the substrate and electrically connected to the first conductive through-via, wherein the substrate is in contact with the insulating encapsulant, wherein a lateral dimension of the substrate is greater than a lateral dimension of the insulating encapsulant (see Fig. 2).
Regarding Claim 2, Yang teaches the semiconductor package as claimed in claim 1, wherein an interface between the first conductive through-via and the second conductive through-via is solder-free (Fig. 2 shows 6 and 22 in direct contact).
Regarding Claim 3, Yang teaches the semiconductor package as claimed in claim 1, further comprising an adhesive layer 14 between the sensor die and the substrate, wherein the sensor die is directly attached to the substrate through the adhesive layer.
Regarding Claim 4, Yang teaches the semiconductor package as claimed in claim 1, wherein outer sidewalls of the insulating encapsulant substantially align with sidewalls of the first redistribution structure (outer walls of 18 and 24 considered to “substantially” align).
Regarding Claim 5, Yang teaches the semiconductor package as claimed in claim 4, wherein the substrate and the second redistribution structure are substantially identical in lateral dimension (8/10 and 2 are considered to “substantially” align).
Regarding Claim 6, Yang teaches the semiconductor package as claimed in claim 1, wherein a landing region of the substrate is uncovered by the insulating encapsulant (see Fig. 2).
Regarding Claim 16, Yang teaches a semiconductor package, comprising:
a substrate comprising a first conductive through-via;
a sensor die disposed on the substrate;
a second conductive through-via disposed on the substrate and electrically connected to the first conductive through-via;
an insulating encapsulant laterally encapsulating the second through-via (see above), wherein a thickness of the insulating encapsulant is greater than a thickness of the sensor die, and the thickness of the insulating encapsulant is substantially equal to a height of the second conductive-via (height of 18 where outer 22 is located is substantially equal); and
a first redistribution structure disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via (See above), and the first redistribution structure comprising a window 40 located above the sensor die.
Regarding Claim 17, Yang teaches the semiconductor package as claimed in claim 16, wherein the substrate is in contact with the insulating encapsulant (See Fig. 2).
Regarding Claim 18, Yang teaches the semiconductor package as claimed in claim16, wherein sidewalls of the first redistribution structure are laterally offset from sidewalls of the substrate (See Fig. 2).
Regarding Claim 19, Yang teaches the semiconductor package as claimed in claim 16, wherein a lateral dimension of the substrate is greater than a lateral dimension of the first redistribution structure (See Fig. 2).
Regarding Claim 20, Yang teaches the semiconductor package as claimed in claim 16, further comprising:
a second redistribution structure 8/10 disposed on the substrate and electrically connected to the first conductive through-via, wherein a laterally dimension of the substrate is greater than a lateral dimension of the insulating encapsulant (See Fig. 2).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20160212852 to Hu et al. (Hu) in view of U.S. Pat. Pub. No. 20120313209 to Oganesian et al. (Oganesian).
Regarding Claim 1, Hu teaches in Fig. 3A at least, a semiconductor package, comprising:
a substrate 30 comprising a first conductive through-via 302;
a sensor die 23 disposed on the substrate;
a second conductive through-via 24 disposed on the substrate and electrically connected to the first conductive through-via;
an insulating encapsulant 20 laterally encapsulating the sensor die and the second through-via;
a first redistribution structure 21 disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via;
and a second redistribution structure 301 disposed on the substrate and electrically connected to the first conductive through-via, wherein the substrate is in contact with the insulating encapsulant,
but does not explicitly teach that a lateral dimension of the substrate is greater than a lateral dimension of the insulating encapsulant.
However, in analogous art, Oganesian teaches a substrate 1 that has a greater lateral dimension than an encapsulant 78 surrounding a sensor die 66. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Oganesian to provide greater flexibility in design and integration, such as including control circuitry 26. Oganesian further similarly teaches a second redistribution layer 34 on the substrate 1.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Regarding Claim 7, Yang teaches the semiconductor package as claimed in claim 1, wherein the first conductive through-via has a first surface in contact with the second conductive through- via and a second surface opposite to the first surface, but does not explicitly teach that a dimension of the first surface is less than a dimension of the second surface.
However, mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled (MPEP 2144.04(IV)(A)). In this case, there is nothing on the record that suggests a significance to the dimension of the first surface.
Claims 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of U.S. Pat. Pub. No. 20170228529 to Huang et al. (Huang).
Regarding Claim 8, Yang teaches a semiconductor package, comprising:
a substrate 2 comprising a first conductive through-via 6;
a sensor die 16 and a second conductive through-via 22 on a first surface of the substrate;
an insulating encapsulant 18 laterally encapsulating the sensor die and the second conductive through-via, and the insulating encapsulant being in contact with the first surface of the substrate;
a front-side redistribution structure 22/24 on the sensor die, the insulating encapsulant and the second conductive through-via, wherein the sensor die is electrically connected to the second conductive through-vias through a first redistribution via (22 contacting 16), a redistribution line 24; and
a back-side redistribution structure 8/10 on a second surface of the substrate, the second surface being opposite to the first surface.
but does not explicitly teach that a second redistribution via, the first redistribution via is higher than the second redistribution via, and a bottom surface of the second redistribution via is lower than a bottom surface of the first redistribution via.
However, in analogous art, Huang teaches a multi-layer redistribution structure 102 for electrical connection to a sensor die 102. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Huang for greater flexibility of design. The person of ordinary skill having the benefit of Yang and Huang may arrange a redistribution layer with any surfaces being higher or lower than another to meet application specific requirements (see MPEP 2144.04(VI)(C)).
Regarding Claim 9, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein an interface between the first conductive through-via and the second conductive through-via is solder-free (see above).
Regarding Claim 10, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein the front-side redistribution structure comprises a first potion overlying the sensor die and a second portion overlying the insulating encapsulant, and the first portion is thicker than the second portion (22 contacting 16 is thicker than 24, for example).
Regarding Claim 11, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein the substrate extends beyond lateral extents of the insulating encapsulant and the front-side redistribution structure (see above).
Regarding Claim 12, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein outer sidewalls of the insulating encapsulant are substantially aligned with outer sidewalls of the front-side redistribution structure (see above).
Regarding Claim 13, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein the first conductive through-via is substantially aligned with the second conductive through-via (see above).
Regarding Claim 14, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein outer sidewalls of the substrate are substantially aligned with outer sidewalls of the back-side redistribution structure (see above).
Regarding Claim 15, Yang and Huang teach the semiconductor package as claimed in claim 8, wherein the back-side redistribution structure is wider than the front-side redistribution structure (see above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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