Prosecution Insights
Last updated: April 19, 2026
Application No. 18/513,644

SEMICONDUCTOR PACKAGE AND FORMING METHOD THEREOF

Non-Final OA §102§103§112
Filed
Nov 20, 2023
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
532 granted / 723 resolved
+5.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 723 resolved cases

Office Action

§102 §103 §112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 1 objected to because of the following informalities: “a laterally dimension” should be “a lateral dimension.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 5 and 10 are rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 1, from which Claim 5 depends, is limited to the substrate being wider than the encapsulant. The first redistribution layer cannot be wider than the encapsulant, so it cannot be substantially the same width as the substrate. It is assumed the second redistribution layer was intended. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim 8, from which Claim 10 depends, is limited to the encapsulant con Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 6 are is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20120313209 to Oganesian et al. (Oganesian). Regarding Claim 1, Oganesian teaches in Fig. 18 at least, a semiconductor package, comprising: a substrate 1 comprising a first conductive through-via 20; a sensor die 66 disposed on the substrate; a second conductive through-via 80 disposed on the substrate and electrically connected to the first conductive through-via; an insulating encapsulant 78 laterally encapsulating the sensor die and the second through-via; a first redistribution structure 84 disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via; and a second redistribution structure 34/36 disposed on the substrate and electrically connected to the first conductive through-via, wherein a lateral dimension of the substrate is greater than a lateral dimension of the insulating encapsulant (see Fig. 18). Regarding Claim 6, Oganesian teaches the semiconductor package as claimed in claim 1, wherein a landing region of the substrate is uncovered by the insulating encapsulant (landing region of the substrate, assumed to be a contact area for the sensor structure 2 of Oganesian, is not covered by the encapsulant 78). Claims 8, 9 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20160212852 to Hu et al. (Hu). Regarding Claim 8, Hu teaches in Fig. 3C at least, a semiconductor package, comprising: a substrate 300 comprising a first conductive through-via 302; a sensor die 23 and a second conductive through-via 24 on a first surface (facing up on page) of the substrate; an insulating encapsulant 20 laterally encapsulating the sensor die and the second conductive through-via, the insulating encapsulant being in contact with the first surface of the substrate, wherein a region of the first surface of the substrate is revealed from the insulating encapsulant (contact pads 22 under sensor die 23 expose the top surface of the substrate 300 from the encapsulant 20); a front-side redistribution structure 21/26 on the sensor die, the insulating encapsulant and the second conductive through-via; and a back-side redistribution structure 301 on a second surface of the substrate, the second surface being opposite to the first surface. Regarding Claim 9, Hu teaches the semiconductor package as claimed in claim 8, wherein an interface between the first conductive through-via and the second conductive through-via is solder-free (no solder taught by Hu). Regarding Claim 12, Hu teaches the semiconductor package as claimed in claim 8, wherein outer sidewalls of the insulating encapsulant are substantially aligned with outer sidewalls of the front-side redistribution structure (21/26 is “substantially aligned” with 20). Regarding Claim 13, Hu teaches the semiconductor package as claimed in claim 8, wherein the first conductive through-via is substantially aligned with the second conductive through-via (see Fig. 3C). Regarding Claim 14, Hu teaches the semiconductor package as claimed in claim 8, wherein outer sidewalls of the substrate are substantially aligned with outer sidewalls of the back-side redistribution structure (see Fig. 3C). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 4, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Oganesian. Regarding Claim 1, Hu teaches in Fig. 3C at least, a semiconductor package, comprising: a substrate 30 comprising a first conductive through-via 302; a sensor die 23 disposed on the substrate; a second conductive through-via 24 disposed on the substrate and electrically connected to the first conductive through-via; an insulating encapsulant 20 laterally encapsulating the sensor die and the second through-via; a first redistribution structure 21/26 disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via; and a second redistribution structure 301 disposed on the substrate and electrically connected to the first conductive through-via, but does not explicitly teach that a laterally dimension of the substrate is greater than a lateral dimension of the insulating encapsulant. However, in analogous art, Oganesian teaches in Fig. 18 at least a first substrate 1 that is wider than an encapsulated 78 sensor die 66. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Oganesian to include further functionality in the first substrate, to fit other devices on the first substrate, or otherwise increase integration. Regarding Claim 2, Hu and Oganesian teach the semiconductor package as claimed in claim 1, wherein an interface between the first conductive through-via and the second conductive through-via is solder-free (first and second vias are bonded through contacts 22). Regarding Claim 4, Hu and Oganesian teach the semiconductor package as claimed in claim 1, wherein the insulating encapsulant and the first redistribution structure are substantially identical in lateral dimension (RDL 21 matches the width of the encapsulant 20). Regarding Claim 5, Hu and Oganesian teach the semiconductor package as claimed in claim 4, wherein the substrate and the first redistribution structure are substantially identical in lateral dimension (see Fig. 18). Regarding Claim 7, Hu and Oganesian teach the semiconductor package as claimed in claim 1, wherein the first conductive through-via has a first surface in contact with the second conductive through-via (although not directly contacting, contacting through pad 22) and a second surface opposite to the first surface, and a dimension of the first surface is less than a dimension of the second surface (first vias 20 of Oganesian are reverse-tapered). Claims 11 and 15 are rejected under 103 over Hu as applied to Claim 8 above and further in view of Oganesian. Regarding Claim 11, Hu and Oganesian teach the semiconductor package as claimed in claim 8, but does not explicitly teach that the substrate extends beyond lateral extents of the insulating encapsulant and the front-side redistribution structure. However, in analogous art, Oganesian teaches in Fig. 18 at least a first substrate 1 that is wider than an encapsulated 78 sensor die 66. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Oganesian to include further functionality in the first substrate, to fit other devices on the first substrate, or otherwise increase integration. Regarding Claim 15, Hu and Oganesian teach the semiconductor package as claimed in claim 8, wherein the back-side redistribution structure is wider than the front-side redistribution structure (see again combination of Hu and Oganesian). Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Oganesian as applied to Claim 1 and further in view of U.S. Pat. Pub. No. 20160268326 to Yu et al. (Yu) Regarding Claim 3, Hu and Oganesian teach the semiconductor package as claimed in claim 1, but do not explicitly teach an adhesive layer between the sensor die and the substrate. However, in analogous art, Yu teaches an adhesive layer 501 for bonding a sensor die 50’. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Yu to securely attach a die. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to Claim 8 and further in view of Yu. Regarding Claim 10, Hu teaches the semiconductor package as claimed in claim 8, further comprising a die-attach film (DAF) or a thermal interface material (TIM) between the sensor die and the substrate. However, in analogous art, Yu teaches an adhesive layer 501, reading on a DAF, for bonding a sensor die 50’. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Yu to securely attach a die. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20180294299 to Baek et al. (Baek) Regarding Claim 16, Baek teaches in Figs. 8-9 at least, a semiconductor package, comprising: a substrate 2500 comprising a first conductive through-via (not numbered); a sensor die 120 disposed on the substrate; a second conductive through-via disposed on the substrate and electrically connected to the first conductive through-via (in Fig. 8, 2100 is described as a “fan out semiconductor package” which may be replaced by the fan out semiconductor package 100A of Fig. 9 for mounting on substrate 2500 of Fig. 8, as “Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific Scimed, Inc. v. Cordis Corp.(Fed. Cir. 2009); an insulating encapsulant 130 laterally encapsulating the second through-via, wherein a thickness of the insulating encapsulant is greater than a thickness of the sensor die (see Fig. 9); and a first redistribution structure 141-143c disposed on the insulating encapsulant, the first redistribution structure being electrically connected to the sensor die and the second conductive through-via, and the first redistribution structure comprising a window 150 located above the sensor die. Regarding Claim 17, Baek teaches the semiconductor package as claimed in claim 16, wherein a height of the second through-via is greater than the thickness of the sensor die (see Fig., 9). Regarding Claim 18, Baek teaches the semiconductor package as claimed in claim 16, wherein sidewalls of the first redistribution structure are laterally offset from sidewalls of the substrate (fan out package 100A is narrower than substrate 2500). Regarding Claim 19, Baek teaches the semiconductor package as claimed in claim 16, wherein a lateral dimension of the substrate is greater than a lateral dimension of the first redistribution structure (fan out package 100A is narrower than substrate 2500). Regarding Claim 20, Baek teaches the semiconductor package as claimed in claim 16, further comprising: a second redistribution structure disposed on the substrate (not numbered, on both sides of 2500) and electrically connected to the first conductive through-via, wherein a laterally dimension of the substrate is greater than a lateral dimension of the insulating encapsulant (see Fig. 8). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Nov 20, 2023
Application Filed
Sep 23, 2025
Examiner Interview (Telephonic)
Feb 10, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 723 resolved cases by this examiner. Grant probability derived from career allow rate.

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