Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 3/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Muller US 2019/0130957 in view of Chu et al. US 9520467.
Re claim 1, Muller teaches a capacitor structure with a fin structure (fig6C), comprising:
a fin structure (112c, fig6c, [115]) located on a substrate (212, fig6B, [114]);
a lower electrode layer (124, fig6C, [119]), a high dielectric constant layer (126 as HfO2, fig6C, [80]) and an upper electrode layer (128t, fig6C, [119]) sequentially stacked on the fin structure;
Muller does not explicitly show an ion doped region located in the substrate below the fin structure, and a top surface of the ion doped region is aligned with a bottom surface of the fin structure.
Chu teaches an ion doped region (region along BB’ between S and D, fig2, col7 line 35-45) located in the substrate below the fin structure, and a top surface of the ion doped region (surface under 100A and between S/D at tail part of dopant profile left side of W4 on C side of line CC’ as in fig5 and 2) is aligned with a bottom surface of the fin structure (top and bottom surface of the doped region as in fig2, 4 and 5 all aligned with center region with W3, fig1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Muller and Chu to dope the region under gate between S/D as in Chu. The motivation to do so is to reduce gate length and tune the threshold voltage to a sufficient high value to eliminate short channel effect (Chu, col8 line 10-15).
Re claim 2, Muller modified above teaches the capacitor structure with a fin structure according to claim 1, wherein the concentration of the ion doped region decreases from a center region to an outside region (Chu, fig4).
Re claim 3, Muller modified above teaches the capacitor structure with a fin structure according to claim 1, wherein the concentration of the ion doped region presents Gaussian distribution (Chu, P3, fig4, col7 line 40-45).
Re claim 4, Muller modified above teaches the capacitor structure with a fin structure according to claim 1, further comprising a dielectric layer (Muller, 240, fig6C, [94]) located on the substrate, and the dielectric layer defines a groove (Muller, space between STI holding channel 122c, fig6c), and part of the fin structure is located in the groove (Muller, fig6C).
Re claim 7, Muller modified above teaches the capacitor structure with a fin structure according to claim 1, wherein the lower electrode layer (Muller, 124, fig6C, [119]), the high dielectric constant layer (Muller, 126 as HfO2, fig6C, [80]) and the upper electrode layer (Muller, 128t, fig6C, [119]) have the same cross-sectional profile from a cross-sectional view (Muller, U shape 124, 126 and 128t, fig6C).
Re claim 9, Muller modified above teaches the capacitor structure with a fin structure according to claim 1, wherein the doped ions in the ion doped region include phosphorus ions and arsenic ions (Muller with channel implant of Chu P or As for NFET or PFET, [93]).
Claim(s) 1, 4-6 , 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda et al. US 2003/0142533 in view of Chu et al. US 9520467.
Re claim 1, Ueda teaches a capacitor structure with a fin structure (fig1-3), comprising:
a fin structure (fin between 5, fig2, [116]) located on a substrate (1, fig2, [116]);
a lower electrode layer (9-13a-13b-14a-14b or 14a or 14a-14b, fig3, [117]), a high dielectric constant layer (16 and 18, fig3, [116]) and an upper electrode layer (17 or 19, fig3, [117]) sequentially stacked on the fin structure;
Ueda does not explicitly show an ion doped region located in the substrate below the fin structure, and a top surface of the ion doped region is aligned with a bottom surface of the fin structure.
Chu teaches a fin structure (fin between STI, fig15) located on a substrate; an ion doped region (region along BB’ between S and D, fig2, col7 line 35-45) located in the substrate below the fin structure, and a top surface of the ion doped region (surface under 100A and between S/D at tail part of dopant profile left side of W4 on C side of line CC’ as in fig5 and 2) is aligned with a bottom surface of the fin structure (top and bottom surface of the doped region as in fig2, 4 and 5 all aligned with center region with W3, fig1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ueda and Chu to dope the region under gate between S/D as in Chu with channel fin formed between STI. The motivation to do so is to reduce gate length and tune the threshold voltage to a sufficient high value to eliminate short channel effect (Chu, col8 line 10-15) and define each with the isolation region to prevent cross talk (Chu, col9 line 60-69).
Re claim 4, Ueda modified above teaches the capacitor structure with a fin structure according to claim 1, further comprising a dielectric layer (Ueda, 5, fig2 and 3, [116]) located on the substrate, and the dielectric layer defines a groove (Ueda, space between 5 holding channel, fig2), and part of the fin structure is located in the groove (Ueda, fig1 and 2).
Re claim 5, Ueda modified above teaches the capacitor structure with a fin structure according to claim 4, wherein the lower electrode layer (9, 13a, 13b, 14a and 14b, fig3, [117]) at least covers a top surface of the dielectric layer (Ueda, 5, fig3, [116]), a top surface of the substrate (Ueda, 1, fig2 and 3, [116]), a top surface and a sidewall of the fin structure (Ueda, 9 cover side surface of fin 1 in contact with 5 and top surface of 1 between 5, fig3).
Re claim 6, Ueda modified above teaches the capacitor structure with a fin structure according to claim 5, further comprising a spacer (Ueda, 11 in contact with 5, fig2) located on a sidewall of the groove (Ueda, space between 5, fig2), and the lower electrode layer covers the spacer (Ueda, 14a and 14b cover part of 11 in contact with 5, fig3).
Re claim 8, Ueda modified above teaches the capacitor structure with a fin structure according to claim 1, further comprising an upper electrode contact structure (Ueda, 19, fig3, [117]) electrically connected to the upper electrode layer (Ueda, 17, fig3, [117]), wherein the lower electrode layer (Ueda, 14a, fig3, [117]) is not located directly below the upper electrode contact structure (Ueda, 19, fig3, [117]).
Re claim 10, Ueda modified above teaches the capacitor structure with a fin structure according to claim 1, further comprising a lower electrode contact structure (Ueda, 9, 13a and 13b, fig3, [116]) located on the fin structure, and the lower electrode contact structure (Ueda, 9, 13a and 13b, fig3, [116]) is electrically connected to the lower electrode layer (Ueda, 14a and 14b, fig3, [117])) through the ion doped region (Ueda, channel region with the doping profile of Chu between 5, fig1 and 3).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812