DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Publication No. 2021/0020602) in view of Yieh et al. (U.S. Publication No. 2016/0079034).
Regarding claim 1¸ Chen teaches a method comprising:
bonding a first device die (Fig. 2A, die SC2) onto a package component (RDL 102), wherein the first device die comprises a semiconductor substrate (substrate 201);
depositing a dielectric liner (Fig. 2B, liner 112) lining sidewalls of the first device die (Fig. 2B);
depositing a dielectric layer (Fig. 2B, dielectric layer 114) on the dielectric liner;
planarizing the dielectric layer and the first device die (Fig. 2C), wherein remaining portions of the dielectric liner and the dielectric layer form a gap-filling region (Fig. 2C); and
forming a redistribution line (Fig. 2, RDL 118) over and electrically connecting to the first device die (Fig. 3).
Chen does not teach performing a first implantation process to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. However, Yieh teaches a SiO2 gap fill layer can have impurities implanted to tune the properties of the layer such as density, stress, etch selectivity and shrinkage (Yieh paragraph [0068]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the SiO2 gap fill layer of Chen could have also had impurities implanted in order to achieve the same tuning effects.
Regarding claim 7¸ Chen in view of Yieh teaches the method of claim 1 further comprising:
bonding a second device die over the first device die (Chen Fig. 11, second die SC2);
depositing an additional dielectric liner lining sidewalls of the second device die (Fig. 11, liner 117);
depositing an additional dielectric layer on the additional dielectric liner (Fig. 11, dielectric layer 115);
planarizing the additional dielectric layer and the second device die (Fig. 11), wherein remaining portions of the additional dielectric liner and the additional dielectric layer form an additional gap-filling region (Fig. 11); and
performing a second implantation process to introduce an additional stress modulation dopant into at least one of the additional dielectric liner and the additional dielectric layer (the same method is executed on the second layer of dies/dielectrics, see Chen paragraph [0049], and therefore under the combination, the implantation step would also be performed on the dielectric 115 of the second layer).
Regarding claim 8¸ Chen in view of Yieh teaches the method of claim 7, wherein the stress modulation dopant is same as the additional stress modulation dopant (the methods would be identical).
Regarding claim 9¸ Chen in view of Yieh teaches the method of claim 1, wherein the first implantation process comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, Er, Yb, and combinations thereof (see Yieh paragraph [0087]).
Regarding claim 10¸ Chen in view of Yieh teaches the method of claim 9, wherein the first implantation process comprises implanting the element selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof (Yieh paragraph [0087]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Yieh, further in view of Hsu et al. (U.S. Publication No. 2020/0395338).
Regarding claim 5¸ Chen in view of Yieh teaches the method of claim 1, but does not teach wherein the first device die comprises a through-via extending into the semiconductor substrate, and wherein a top end of the through-via is revealed after the dielectric layer is planarized.
However, Hsu teaches a similar package in which the die has TSVs (Hsu Fig. 4D, TSV), which are revealed after planarizing the dielectric layer (Hsu Fig. 4D, paragraph [0030], dielectric layer E is planarized to reveal top surface of die S, which therefore also reveals the TSVs). It would have been obvious to a person of skill in the art at the time of the effective filing date that TSVs could have been included because they allow for signals to go directly through the chip to overlying lines, reducing resistance and communication time by not requiring re-routing through the RDL.
Allowable Subject Matter
Claims 21-29 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 21-25, the prior art, alone or in combination, fails to teach or suggest wherein the second portion of the dielectric liner is implanted with a dopant having a first concentration, and wherein a second concentration of the dopant in the second portion of the top dielectric layer of the package component is lower than the first concentration.
Regarding claims 26-29, the prior art, alone or in combination, fails to teach or suggest wherein the forming the second portion comprises implanting a dopant therein, and the dopant has a first peak concentration in the second portion.
Claims 2-4, 6 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2-4, the prior art, alone or in combination, fails to teach or suggest wherein the first implantation process is performed on the dielectric liner, and is performed before the dielectric layer is deposited.
Regarding claim 6, the prior art, alone or in combination, fails to teach or suggest after the first device die is bonded to the package component and before the dielectric liner is deposited, performing a second implantation process to implant a top dielectric layer of the package component.
Regarding claim 11, the prior art, alone or in combination, fails to teach or suggest wherein a peak concentration of the element is in the dielectric liner.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVAN G CLINTON/Primary Examiner, Art Unit 2899
Prosecution Insights