DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I and Species II in the reply filed on 4/24/2026 is acknowledged. The traversal is on the ground(s) that the election/restriction requirement fails to show that the identified species are independent and distinct, a showing of "serious burden" has not been made, the election/restriction requirement is based on the incorrect assertion that the identified species are mutually exclusive and the demarcation between species is arbitrary, without regard to common aspects between species (Remarks 8-11). This is not found persuasive because as previously detailed in the requirement for restriction/election mailed on 2/26/2026 Species I (as disclosed in Figure 6 of the Drawings) and Species II (as disclosed in Figure 8 of the Drawings) are independent or distinct, because Species I requires the JFET region to extend deeper into the semiconductor layer structure than the trench shielding region, while Species II requires the trench shielding region to extend deeper into the semiconductor layer structure than the JFET region. These configurations of the depth of the trench shielding region in relation to the depth of the JFET region are not compatible with one another. It is not possible for both the JFET region to extend deeper into the semiconductor layer structure than the trench shielding region and the trench shielding region to extend deeper into the semiconductor layer structure than the JFET region, and thereby these configurations are mutually exclusive from one another. Additionally, there would be a burden to search for both of the features of Species I and II, because the features, which are mutually exclusive from one another, require a different field of search, such as searching different classes/subclasses or electronic resources, or employing different search strategies or search queries, so searching for the features will not be coextensive.
The requirement is still deemed proper and is therefore made FINAL.
Claims 8, 23, 25, 30-31 and 33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group/Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 4/24/2026.
A. Prior-art rejections based at least in part by Tanaka
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 2021/0184030 A1, hereinafter “Tanaka”).
Regarding independent claim 1, Figure 35 of Tanaka discloses a semiconductor device, comprising:
a semiconductor layer structure comprising a junction field-effect transistor (JFET) region 25b (“high-concentration region”- ¶0256) of a first conductivity type, a well region 26 (“body region”- ¶0060) of a second conductivity type on the JFET region 25b, a source region 27 (“source region”- ¶0060) of the first conductivity type on the well region 26 and a plurality of support shields 28 (“electric field relaxation regions”- ¶0061) of the second conductivity type, the support shields 28 being spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extending through the source region 27, the well region 26 and the JFET region 25b; and
a trenched gate structure 16/18 (collectively 16 “gate electrodes” and 18 (“gate insulating layers”- ¶0059) formed in the semiconductor layer structure between a pair of adjacent support shields 28,
wherein edges (i.e., the edges of 25b, 26 and 27 along gate structure 16/18) of at least two of the JFET region 25b, the well region 26 and the source region 27 are aligned in a second direction perpendicular to the first direction.
Regarding claim 2, Figure 35 of Tanaka discloses the semiconductor device further comprising a trench shielding region 45 (“bottom regions”- ¶0256) of the second conductivity type formed in the semiconductor layer structure below the trenched gate structure 16/18.
Regarding claim 3, Figure 35 of Tanaka discloses wherein the first conductivity type is N-type and the second conductivity type is P-type (¶¶0059-0061, 0256).
Regarding claim 6, Figure 35 of Tanaka discloses wherein the semiconductor layer structure comprises silicon carbide (¶0060).
Regarding claim 7, Figure 35 of Tanaka discloses wherein the semiconductor layer structure further comprises a trench shielding region 45 (“bottom regions”- ¶0256) having the second conductivity type below the trenched gate structure 16/18.
Regarding claim 12, Figure 35 of Tanaka discloses wherein the plurality of support shields 28 extend in the second direction deeper into the semiconductor layer structure than the JFET region 25b.
Regarding claim 13, Figure 35 of Tanaka discloses wherein the trenched gate structure 16/18 comprises:
an insulating layer 18 on inner wall and bottom surfaces of the trenched gate structure 16/18; and
a gate 16 on the insulating layer 18 and at least partially filling the trenched gate structure 16/18.
B. Prior-art rejections based at least in part by Martinez
Claim Rejections - 35 USC § 102
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Martinez-Limia et al. (US 2025/0169144 A1, hereinafter “Martinez”).
Regarding independent claim 1, Figure 2B of Martinez discloses a semiconductor device, comprising:
a semiconductor layer structure comprising a junction field-effect transistor (JFET) region 9 (“n-doped region”- ¶0036) of a first conductivity type, a well region 6 (“p-doped body region”- ¶0036) of a second conductivity type on the JFET region 9, a source region 7 (“n+-doped source region”- ¶0036) of the first conductivity type on the well region 6 and a plurality of support shields 8 (“p+-doped region”- ¶0036) of the second conductivity type, the support shields 8 being spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extending through the source region 7, the well region 6 and the JFET region 9; and
a trenched gate structure 3 (“conductive material… gate electrode”- ¶0035) formed in the semiconductor layer structure between a pair of adjacent support shields 8,
wherein edges of at least two of the JFET region 9, the well region 6 and the source region 7 are aligned in a second direction perpendicular to the first direction.
Regarding claim 4, Figure 2B of Martinez discloses wherein each of the JFET region 9, the well region 6 and the source region 7 is configured having an edge that is aligned, in the second direction, with the edge of the support shields 8 facing the trenched gate structure 3.
Regarding claim 5, Figure 2B of Martinez discloses wherein each of the JFET region 9, the well region 6 and the source region 7 is configured having an edge that is aligned, in the direction perpendicular to the upper surface of the semiconductor layer structure, with the edge of the support shields 8 facing the trenched gate structure 3.
C. Prior-art rejections based at least in part by Kim
Claim Rejections - 35 USC § 102
Claims 1-3, 6-7, 9, 12-16 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2023/0307529 A1, hereinafter “Kim”).
Regarding independent claim 1, Figure 2 of Kim discloses a semiconductor device, comprising:
a semiconductor layer structure comprising a junction field-effect transistor (JFET) region 175 (“JFET region”- ¶¶0065, 0067) of a first conductivity type, a well region 170 (“well regions”- ¶0067) of a second conductivity type on the JFET region 175, a source region 160 (“source regions”- ¶0067) of the first conductivity type on the well region 170 and a plurality of support shields 240b (“shielding structures”- ¶0072) of the second conductivity type, the support shields 240b being spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extending through the source region 160, the well region 170 and the JFET region 175; and
a trenched gate structure 182/184 (collectively 182 “gate insulating layer” and 184 “gate electrodes”- ¶0066) formed in the semiconductor layer structure between a pair of adjacent support shields 240b,
wherein edges (i.e., the edges of 175, 170 and 160 along the side of gate structure 182/184) of at least two of the JFET region 175, the well region 170 and the source region 160 are aligned in a second direction perpendicular to the first direction.
Regarding claim 2, Figure 2 of Kim discloses the semiconductor device further comprising a trench shielding region 240a (“shielding structures”- ¶0072) of the second conductivity type formed in the semiconductor layer structure below the trenched gate structure 182/184.
Regarding claim 3, Figure 2 of Kim discloses wherein the first conductivity type is N-type and the second conductivity type is P-type (¶¶0065-0067, 0072).
Regarding claim 6, Figure 2 of Kim discloses wherein the semiconductor layer structure comprises silicon carbide (¶0065).
Regarding claim 7, Figure 2 of Kim discloses wherein the semiconductor layer structure further comprises a trench shielding region 240a (“shielding structures”- ¶0072) having the second conductivity type below the trenched gate structure 182/184.
Regarding claim 9, Figure 2 of Kim discloses wherein the trench shielding region 240a extends in the second direction deeper into the semiconductor layer structure than the JFET region 175.
Regarding claim 12, Figure 2 of Kim discloses wherein the plurality of support shields 240a extend in the second direction deeper into the semiconductor layer structure than the JFET region 175.
Regarding claim 13, Figure 2 of Kim discloses wherein the trenched gate structure 182/184 comprises:
an insulating layer 182 on inner wall and bottom surfaces of the trenched gate structure 182/184; and
a gate 184 on the insulating layer 182 and at least partially filling the trenched gate structure 182/184.
Regarding independent claim 14, Figure 2 of Kim discloses a semiconductor device, comprising:
a semiconductor layer structure comprising a junction field-effect transistor (JFET) region 175 (“JFET region”- ¶¶0065, 0067) of a first conductivity type, a well region 170 (“well regions”- ¶0067) of a second conductivity type on the JFET region 175, a source region 160 (“source regions”- ¶0067) of the first conductivity type on the well region 170; and
a trenched gate structure 184 (“gate electrodes”- ¶0066) formed in the semiconductor layer structure between a pair of adjacent support shields 240b (“shielding structures”- ¶0072), the trenched gate structure 184 including a gate electrode 184,
wherein the JFET region 175 does not extend completely underneath the trenched gate structure 184.
Regarding claim 15, Figure 2 of Kim discloses wherein the JFET region 175 does not vertically overlap the gate electrode 184.
Regarding claim 16, Figure 2 of Kim discloses wherein the semiconductor layer structure further comprises a trench shielding region 240a (“shielding structures”- ¶0072) having the second conductivity type underneath the trenched gate structure 184.
Regarding claim 21, Figure 2 of Kim discloses wherein the JFET region 175 comprises a selectively implanted layer in the semiconductor layer structure (¶0082).
Note, regarding the claim limitation “a selectively implanted layer in the semiconductor layer structure” (emphasis added) which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same.
Allowable Subject Matter
Claims 10-11 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10 (which claim 11 depends from), the prior art of record including Tanaka, Martinez and/or Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the semiconductor layer structure further comprises a second JFET region having the first conductivity type below the trench shielding region”.
Regarding claim 19, the prior art of record including Tanaka, Martinez and/or Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the semiconductor layer structure further comprises a second JFET region of the first conductivity type below the trench shielding region”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Alexandro et al. (US 2014/0361349 A1), which discloses a semiconductor device comprising a trenched gate structure within a JFET region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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