CTFR 18/514,089 CTFR 101466 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Mallik et al. (US Patent Pub (20230207525 A1) . Regarding Claim 1, Mallik teaches a manufacturing method, comprising: providing a first assembly including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by hybrid bonding (Fig. 4, first assembly 104 including first semiconductor chip 108 and second semiconductor chip 110 stacked on 108 and electrically connected to the first semiconductor chip by hybrid bonding (Paragraph 0033. While paragraph 0033 references Fig. 1, the elements are referred to in the same manner)); providing a second assembly including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip by hybrid bonding, wherein a lateral surface of the first semiconductor chip is aligned with a lateral surface of the second semiconductor chip and is aligned with a lateral surface of the third semiconductor chip (Fig. 4, second assembly 106 including third semiconductor chip 114 and fourth semiconductor chip 116, which is electrically connected to 106 via hybrid bonding (paragraph 0033). A lateral surface 144 of 108 is aligned with a lateral surface 146 of 110, and is aligned with a lateral surface 142 of 114); and electrically connecting the second assembly to the first assembly through a plurality of bumps (Fig. 4, second assembly 106 electrically connected to first assembly 104 through a plurality of bumps 120 (paragraph 0033)) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim (s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik (US Patent Pub 20230207525 A1, Embodiment of Figure 4, hereafter referred to as Mallik 4) as applied to claim 1 above, and further in view of Mallik (US Patent Pub 20230207525 A1, Embodiment of Figure 8, hereafter referred to as Mallik 8) and Knickerbocker et al. (US Patent Pub 20200161230 A1) . Regarding Claim 2, Mallik 4 teaches the method of Claim 1. Mallik 4 fails to teach forming an underfill in a space between the second assembly and the first assembly to cover the plurality of bumps. However, Mallik 8 teaches forming an underfill in a space between the second assembly and the first assembly to cover the plurality of bumps (Mallik 8, Fig. 8, underfill 802 (portion of 802 directly underneath the second assembly 106 covering the plurality of bumps) formed between the first assembly 104 and the second assembly 106, covering the plurality of bumps 120). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 8 into Mallik 4 by forming an underfill in a space between the second assembly and the first assembly to cover the plurality of bumps. The ordinary artisan would have been motivated to modify Mallik 4 in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (paragraph 0059), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (paragraph 002). While Mallik 8 in view of Mallik 6 teaches all of the limitations described in claim 2 above, Mallik fails to specifically teach a thermal conductivity of the underfill is greater than a thermal conductivity of the second semiconductor chip. However, Knickerbocker teaches a method of forming a stacked semiconductor memory device wherein a thermal conductivity of the underfill is greater than a thermal conductivity of the second semiconductor chip (Knickerbocker, paragraph 0101 teaches underfills formed of materials with higher thermal conductivity may be used such as Aluminum Nitride. Cited NPL (Cheng et al., pg 5 column 1 lines 6-9) teaches Aluminum Nitride has a thermal conductivity of 321 W m -1 K -1 . Applicant’s own specification (paragraphs 0031-0032) teaches the second semiconductor chip, which is mostly comprised of the second base portion, can be formed Silicon, which other cited NPL (MatWeb) reports as having a thermal conductivity of 124 W m -1 K -1 ). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Knickerbocker into Mallik 4 in view of Mallik 8 by forming an underfill such that a thermal conductivity of the underfill is greater than a thermal conductivity of the second semiconductor chip. The ordinary artisan would have been motivated to modify Mallik 4 in view of Mallik 8 the manner set forth above for at least the purpose of improving heat transfer (Knickerbocker, paragraph 0101). Regarding Claim 3, Mallik 4 teaches the method of Claim 1, further comprising: electrically connecting the first assembly to a base semiconductor chip via a plurality of electrical connectors (Mallik 4, Fig. 4, first assembly 104 electrically connected base semiconductor chip via a plurality of electrical connectors 122 (paragraph 0033)); Mallik 4 fails to teach the formation of a second underfill in a space between the first assembly and the base semiconductor chip to cover the plurality of electrical connectors. However, Mallik 8 teaches the formation of a second underfill in a space between the first assembly and the base semiconductor chip to cover the plurality of electrical connectors (Mallik 8, Fig. 8, second underfill 804 (portion of 804 in between first assembly 104 and base semiconductor chip 102), which fills the space between the first assembly and the base semiconductor chip to cover the plurality of electrical connectors). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 8 into Mallik 4 by forming a second underfill in a space between the first assembly and the base semiconductor chip to cover the plurality of electrical connectors. The ordinary artisan would have been motivated to modify Mallik 4 in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (paragraph 0059), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (paragraph 002). While Mallik 8 in view of Mallik 6 teaches all of the limitations described in claim 3 above, Mallik fails to specifically teach a thermal conductivity of the second underfill is greater than a thermal conductivity of the first semiconductor chip. However, Knickerbocker teaches a method of forming a stacked semiconductor memory device wherein a thermal conductivity of the underfill is greater than a thermal conductivity of the first semiconductor chip (Knickerbocker, paragraph 0101 teaches underfills formed of materials with higher thermal conductivity may be used such as Aluminum Nitride. Cited NPL (Cheng et al., pg 5 column 1 lines 6-9) teaches Aluminum Nitride has a thermal conductivity of 321 W m -1 K -1 . Applicant’s own specification (paragraphs 0019-0020) teaches the first semiconductor chip, which is mostly comprised of the first base portion, can be formed Silicon, which other cited NPL (MatWeb) reports as having a thermal conductivity of 124 W m -1 K -1 ). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Knickerbocker into Mallik 4 in view of Mallik 8 by forming an underfill such that a thermal conductivity of the second underfill is greater than a thermal conductivity of the first semiconductor chip. The ordinary artisan would have been motivated to modify Mallik 4 in view of Mallik 8 the manner set forth above for at least the purpose of improving heat transfer (Knickerbocker, paragraph 0101). Regarding Claim 4, Mallik 4 in view of Mallik 8 and Knickerbocker teach the method of Claim 3, further comprising: forming an encapsulant to encapsulate a top surface of the base semiconductor chip, the second underfill, the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip, wherein the encapsulant is in direct contact with the lateral surface of the first semiconductor chip, the lateral surface of the second semiconductor chip, and the lateral surface of the third semiconductor chip (Mallik 8, the encapsulant (124/126/portions of 802 and 804 not beneath the third semiconductor chip 114 and the first semiconductor chip 108) encapsulates the top surface of the base semiconductor chip 102, the second underfill (portion of 804 in between first assembly 104 and base semiconductor chip 102), the first semiconductor chip 108, the second semiconductor chip 110, the third semiconductor chip 114, and the fourth semiconductor chip 116. The encapsulant (124/126/portions of 802 and 804 not beneath the third semiconductor chip 114 and the first semiconductor chip 108) is in direct contact with the lateral surface 114 of 108, the lateral surface 146 of 110, and the lateral surface 142 of the third semiconductor chip 114). Response to Arguments Applicant’s arguments with respect to claim(s) 1-4 have been considered but are moot in view of the new grounds of rejection as applied above. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.R.G./Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/514,089 Page 2 Art Unit: 2899 Application/Control Number: 18/514,089 Page 3 Art Unit: 2899 Application/Control Number: 18/514,089 Page 4 Art Unit: 2899 Application/Control Number: 18/514,089 Page 5 Art Unit: 2899 Application/Control Number: 18/514,089 Page 6 Art Unit: 2899 Application/Control Number: 18/514,089 Page 7 Art Unit: 2899 Application/Control Number: 18/514,089 Page 8 Art Unit: 2899 Application/Control Number: 18/514,089 Page 9 Art Unit: 2899
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