Prosecution Insights
Last updated: October 04, 2026
Application No. 18/514,126

Chamfered Die of Semiconductor Package and Method for Forming the Same

Non-Final OA §102§103
Filed
Nov 20, 2023
Priority
Jan 29, 2020 — provisional 62/967,245 +2 more
Examiner
ANDERSON, WILLIAM H
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
5 (Non-Final)
85%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
188 granted / 221 resolved
+17.1% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
46 currently pending
Career history
261
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
52.9%
+12.9% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 221 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 8 is objected to because of the following informalities: “,,” in line 5. For the sake of compact prosecution, claim 8 is interpreted in the instant Office action as follows: “,,” is found to be a typographical error and is believed to be equivalent to “,”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks. Claims 8-9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210125960 A1) in view of Kurose (US 20190057874 A1) and Liu (US 9837366 B1). Regarding independent claim 8, Huang discloses a method of manufacturing a semiconductor device, the method comprising: forming a first die (Fig. 1B: 130), wherein forming the first die comprises chamfering a first corner of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate (131) and a seal ring over the semiconductor substrate,, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view; encapsulating the first die with an encapsulant (Fig. 150); and forming a redistribution structure (Fig. 1C: 170) over the encapsulant and the first die (directly “over”), wherein forming the redistribution structure comprises forming layers of metallization patterns (174) and dielectric layers (172) therebetween; and after forming the redistribution structure over the encapsulant and the first die, removing a material from the redistribution structure and a material from the encapsulant to form a hole (Fig. 1D: 190) through the redistribution structure and the encapsulant (completely “through”), the hole being adjacent the chamfered first corner of the first die in a plan view (Note: Fig. 2A shows the arrangement of the “hole” being “adjacent the […] first corner of the first die in a plan view” without chamfering). Illustrated below are Figs. 1F and 2A of Huang. PNG media_image1.png 376 750 media_image1.png Greyscale PNG media_image2.png 525 597 media_image2.png Greyscale Huang fails to teach “wherein forming the first die comprises chamfering a first corner of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate,, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view;” and “the hole being adjacent the chamfered first corner of the first die in a plan view”. Kurose discloses a method of manufacturing a semiconductor device, the method comprising: forming a first die (Fig. 6: die 44), wherein forming the first die comprises chamfering a first corner (See annotated Fig. 6 for corner designation) of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate (selecting the embodiment of Fig. 11: insulating layer 100;(102; [0075]: “wafer” in combination with [0052]: “wafer…silicon”) Modifying the method of Huang by forming the first die in the way disclosed by Kurose would arrive at the claimed method and chamfered first corner configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the die is a semiconductor die (Huang: Fig. 1B: die 130; Kurose: Fig. 6: die 44). Kurose provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed die formation method because it would reduce manufacturing damage, by reducing chips and cracks during formation of the die ([0049]: “the sides of the die will have no chips or cracks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and insulating layer configuration because it would reduce manufacturing damage. MPEP 2143 (I)(G). Illustrated below is a marked and annotated figure of Fig. 6, and Fig. 11 of Kurose. PNG media_image3.png 340 376 media_image3.png Greyscale PNG media_image4.png 245 545 media_image4.png Greyscale Huang in view of Kurose fails to teach “wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate,, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view”. Liu a method wherein the first die (Fig. 3I: 310) comprises a semiconductor substrate (310) and a seal ring (326) over the semiconductor substrate, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view (Fig. 5: linear edges of the seal ring at corners of 162). Modifying the method of Huang and Kurose by having the first die (of Huang/Kurose) comprise a seal ring (of Liu) over the semiconductor substrate would provide an octagonal seal ring configured among an octagonal die surface (of Huang/Kurose), and thus arrive at the claimed seal ring configuration “wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate,, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view”. Liu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the seal ring in the method because it would protect the device during manufacture, thereby enhancing manufacturing yield (col. 4, line 64-col. 5, line 23: “can stop undesirable damaging”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Liu does not teach the inclusion of the seal ring having any special requirements or changes to the die to enable the inclusion. Therefore, the claimed seal ring configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it would protect the device from manufacturing defects, thereby enhancing manufacturing yield. MPEP 2143 (I)(G). Regarding claim 9, Huang in view of Kurose and Liu discloses the method of claim 8, wherein chamfering the first corner of the first die comprises using a laser saw (Kurose: [0066]: “a laser”). Regarding claim 11, Huang in view of Kurose and Liu discloses the method of claim 8 (Kurose: Fig. 11), wherein chamfering the first corner of the first die comprises forming a rectangular chamfered surface (the chamfer formed by groove 104 appears substantially vertical, therefore the resultant shape of the die in Fig. 6 would be a substantially vertical rectangle). Regarding claim 12, Huang in view of Kurose and Liu discloses the method of claim 8 (Kurose: Fig. 11), wherein chamfering the first corner of the first die comprises forming a trapezoidal chamfered surface (the chamfer formed by groove 104 appears substantially vertical, therefore the resultant shape of the die in Fig. 6 would be a substantially vertical rectangle. Note: the plain and ordinary meaning of trapezoid, consistent with the inclusive definition, i.e., a quadrilateral having at least one pair of parallel sides; thus the rectangular chamfered surface is a trapezoid). Regarding claim 13, Huang in view of Kurose and Liu discloses the method of claim 8, wherein the seal ring is disposed in an insulating layer (Liu: Fig. 3I: 330) over the semiconductor substrate (310), wherein the seal ring further extends into an interconnect structure (320) that is disposed between the insulating layer and the semiconductor substrate (sandwiched between), wherein chamfering the first corner of the first die comprises forming a first chamfered surface (330 at 312) and a second chamfered surface (320 at 312) abutting the first chamfered surface (vertically abutting), wherein the first chamfered surface is a surface of the insulating layer (this is the selected surface shown in Fig. 3I), and wherein the second chamfered surface is a surface of the interconnect structure (this is the selected surface shown in Fig. 3I). Regarding claim 14, Huang in view of Kurose and Liu discloses the method of claim 8 (Huang: Fig. 1F), further comprising attaching a thermal module (220) to the redistribution structure with a bolt (230), the thermal module being on a back side of the first die opposite the redistribution structure (module 220 and RDL 170 are on opposing sides of die 130), the bolt extending through the hole (fully through the hole 190). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lai, Kurose, and Liu as applied to claim 8 above, and further in view of Yeh (US 10096578 B1). Regarding claim 10, Huang in view of Kurose and Liu teaches the method of claim 8, but fails to teach “wherein chamfering the first corner of the first die comprises forming a triangular chamfered surface”. Yeh teaches chamfering the first corner of the first die (Fig. 1C: corner of die 13) comprises forming a triangular chamfered surface (surface 136). Modifying the method of Huang, Kurose, and Liu by including the additional chamfering technique of Yeh would arrive at the claimed chamfering method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the first die is an encapsulated semiconductor die (Yeh: Fig. 1C: encapsulant 14 on die 13; Huang: Fig. 1B: encapsulant 150 on die 130). Yeh provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the additional chamfering technique in that it would prevent the device from cracking by relieving stress in the device (col. 4, lines 51-67: “can provide for a release or redistribution of stress in the package body”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chamfering method configuration because it would relieve stress in the device. MPEP 2143 (I)(G). Claims 15-16, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kurose. Regarding independent claim 15, Huang discloses a method of manufacturing a semiconductor device, the method comprising: forming a first die (Fig. 1B: one of 130; See Fig. 2A for top-down view) with a chamfered first corner, a second die (Fig. 1B: one of 130; See Fig. 2A for plan view) with a chamfered first corner, a third die (Fig. 1B: one of 130; See Fig. 2A for plan view) with a chamfered first corner, and a fourth die (Fig. 1B: one of 130; See Fig. 2A for plan view) with a chamfered first corner; encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant (150), wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view (this shape is cited with respect to the die corners, without citing chamfered corners, See annotated Fig. 2A for shape designation), the encapsulant filling the quadrilateral shape region; forming a redistribution structure (Fig. 1C: 170) on the encapsulant, the first die, the second die, the third die, and the fourth die; and after forming the redistribution structure on the encapsulant, the first die, the second die, the third die, and the fourth die, removing a material from the redistribution structure and a material from the encapsulant to form a hole (Fig. 1D: 190) extending through (completely “through”) the redistribution structure and the encapsulant, the hole being disposed in the quadrilateral shape region. Huang fails to teach chamfered corners of the dies. Thus, Huang fails to teach: “forming a first die with a chamfered first corner, a second die with a chamfered first corner, a third die with a chamfered first corner, and a fourth die with a chamfered first corner; encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant, wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view, the encapsulant filling the quadrilateral shape region;” Kurose discloses a method of manufacturing a semiconductor device, the method comprising: forming a first die (Fig. 6: die 44) with a chamfered first corner (See annotated Fig. 6 for corner designation), a second die with a chamfered first corner (Fig. 6: a duplicate of die 44 and the designated corner, duplicates are shown), a third die with a chamfered first corner (Fig. 6: a duplicate of die 44 and the designated corner, duplicates are shown), and a fourth die with a chamfered first corner (Fig. 6: a duplicate of die 44 and the designated corner, duplicates are shown). Modifying the method of Huang by forming the first, send, third, and fourth dies in the way disclosed by Kurose would arrive at the claimed method and chamfered first corners configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the dies are semiconductor dies (Huang: Fig. 1B: die 130; Kurose: Fig. 6: die 44). Kurose provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed die formation method because it would reduce manufacturing damage, by reducing chips and cracks during formation of the die ([0049]: “the sides of the die will have no chips or cracks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and corner configuration because it would reduce manufacturing damage. MPEP 2143 (I)(G). Regarding claim 16, Huang in view of Kurose discloses the method of claim 15 (Kurose: Fig. 6), wherein the chamfered first corner of the first die comprises a linear edge (See annotated Fig. 6) in the top-down view. Regarding claim 18, Huang in view of Kurose discloses the method of claim 15 (Kurose: Fig. 6), wherein the first die further comprises a chamfered second corner, a chamfered third corner, and a chamfered fourth corner (all four corners are chamfered). Regarding claim 19, Huang in view of Kurose discloses the method of claim 15 (Huang: Figs. 1F and 2A), further comprising: inserting a bolt (230) through the hole, wherein the bolt overlaps (“overlaps” by at least some amount in some direction) a first space occupied by a first corner of the first die prior to chamfering the first corner of the first die to form the chamfered first corner of the first die. Regarding claim 20, Huang in view of Kurose discloses the method of claim 19 (Huang: Figs. 1F and 2A), wherein the bolt further overlaps (“overlaps” by at least some amount in some direction) a second space occupied by a first corner of the second die prior to chamfering the first corner of the second die to form the chamfered first corner of the second die. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Kurose as applied to claim 15 above, and further in view of Yeh. Regarding claim 17, Huang in view of Kurose discloses the method of claim 15, but fails to teach “wherein the chamfered first corner of the first die comprises an inverted corner in the top-down view”. Yeh teaches chamfering the first corner of the first die (Fig. 1C: corner of die 13) wherein the chamfered first corner of the first die comprises an inverted corner in the top-down view (surfaces 135/136 intersect at an inverted corner, and this intersection is visible in top-down view). Modifying the method of Huang in view of Kurose by including the additional chamfering technique of Yeh would arrive at the claimed chamfering method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the first die is an encapsulated semiconductor die (Yeh: Fig. 1C: encapsulant 14 on die 13; Huang: Fig. 1F: encapsulant 150 on die 130). Yeh provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the additional chamfering technique in that it would prevent the device from cracking by relieving stress in the device (col. 4, lines 51-67: “can provide for a release or redistribution of stress in the package body”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chamfering method configuration because it would relieve stress in the device. MPEP 2143 (I)(G). Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Huang, Kurose, and Yeh as applied to claim 16 above, and further in view of Liu. Regarding claim 22, Huang in view of Kurose and Yeh discloses the method of claim 16, but fails to teach “the first die comprises a seal ring in an insulating layer, and wherein the linear edge of the chamfered first corner of the first die is parallel to a linear edge of the seal ring in a top-down view”. Liu discloses a method, the first die (Fig. 3I: 310) comprises a seal ring (326) in an insulating layer (320/330), and wherein the linear edge of the chamfered first corner of the first die is parallel to a linear edge of the seal ring in a top-down view (Fig. 5: linear edges of the seal ring at corners of 162). Modifying the method of Huang and Kurose by having the first die (of Huang/Kurose) comprise a seal ring (of Liu) in an insulating layer would provide an octagonal seal ring configured among an octagonal die surface (of Huang/Kurose), and thus arrive at the claimed seal ring configuration “the first die comprises a seal ring in an insulating layer, and wherein the linear edge of the chamfered first corner of the first die is parallel to a linear edge of the seal ring in a top-down view”. Liu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the seal ring in the method because it would protect the device during manufacture, thereby enhancing manufacturing yield (col. 4, line 64-col. 5, line 23: “can stop undesirable damaging”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Liu does not teach the inclusion of the seal ring having any special requirements or changes to the die to enable the inclusion. Therefore, the claimed seal ring configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it would protect the device from manufacturing defects, thereby enhancing manufacturing yield. MPEP 2143 (I)(G). Allowable Subject Matter Claims 1-5 and 7 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the allowable subject matter of claims 1-5 and 7 is the inclusion of the limitation “wherein in a cross-sectional view, a portion of the encapsulant fills a space that vertically overlaps the die, wherein the space that vertically overlaps the die extends continuously from a beveled sidewall of the chamfered corner in the insulating layer to a bottom surface of the redistribution structure along a line perpendicular to a top surface of the die, and wherein the beveled sidewall of the chamfered corner directly contacts the bottom surface of the redistribution structure in the cross-sectional view” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “beveled sidewall”, “directly contacts”, and “redistribution structure” in combination with all other limitations in claim 1. The features “beveled sidewalls” and “encapsulant” were found in the prior art; and “directly contacts” and “vertically overlaps” were separately found in the prior art; however, the prior art did teach or suggest these features being combined in the way claimed. Response to Arguments Applicant's arguments filed 9/4/2026 have been fully considered but they are not persuasive. Applicant argues: Applicant argues with respect to claims 8 and 15 that “Lai does not qualify as prior art”. Remarks at pg. 8. Examiner’s reply: The examiner thanks Applicant for clarifying the record regarding Lai and 102(b)(2)(c). Accordingly, all rejections based upon Lai have been withdrawn. However, other prior art (Huang) is relied upon in the instant Office action that presently qualifies as prior art under 102(a)(2), there being no remarks of record to the contrary. Additional similar references that also presently qualify as prior art under 102(a)(2), and made of record in the Office action mailed 5/7/2026, have been made of record again in the instant Office action to promote compact prosecution and clarity of the record. MPEP 717.02(a): Invoking the Prior Art Exception under 35 U.S.C. 102(b)(2)(C): (I): Common Ownership: In order to invoke common ownership to except a disclosure as prior art, the applicant (or the patent owner) must provide a statement that the disclosure of the subject matter on which the rejection is based and the claimed invention were owned by the same person or subject to an obligation of assignment to the same person not later than the effective filing date of the claimed invention. The statement should either be on or begin on a separate sheet and must not be directed to other matters (37 CFR 1.4(c) ). The statement must be signed in accordance with 37 CFR 1.33(b). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lai (US 20200243429 A1) discloses “after forming the redistribution structure (112) over the encapsulant (110) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 9) to form a hole (144) through the redistribution structure and the encapsulant”. Yu (US 20200411488 A1) discloses “after forming the redistribution structure (86) over the encapsulant (80) and the first die (66), removing a material from the redistribution structure and a material from the encapsulant (Fig. 21) to form a hole (98) through the redistribution structure and the encapsulant”. Lai (US 20200212018 A1) discloses “after forming the redistribution structure (430) over the encapsulant (406) and the first die (405), removing a material from the redistribution structure and a material from the encapsulant (28) to form a hole (442) through the redistribution structure and the encapsulant”. Chun (US 20200395257 A1) discloses “after forming the redistribution structure (108) over the encapsulant (106) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 13) to form a hole (148) through the redistribution structure and the encapsulant”. Chun (US 20200185304 A1) discloses “after forming the redistribution structure (108) over the encapsulant (106) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 12) to form a hole (148) through the redistribution structure and the encapsulant”. Yu (US 20200006252 A1) discloses “after forming the redistribution structure (56) over the encapsulant (38) and the first die (26), removing a material from the redistribution structure and a material from the encapsulant (Fig. 9) to form a hole (the hole for bolt 69) through the redistribution structure and the encapsulant”. Lai (US 20200243494 A1) discloses “after forming the redistribution structure (110) over the encapsulant (106) and the first die (102), removing a material from the redistribution structure and a material from the encapsulant (Fig. 11C) to form a hole (160) through the redistribution structure and the encapsulant”. Yu (US 20200203301 A1) discloses “after forming the redistribution structure (110) over the encapsulant (108) and the first die (106A), removing a material from the redistribution structure and a material from the encapsulant (Fig. 5) to form a hole (TH) through the redistribution structure and the encapsulant”. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Show 4 earlier events
Sep 24, 2025
Response after Non-Final Action
Nov 24, 2025
Request for Continued Examination
Nov 29, 2025
Response after Non-Final Action
Jan 20, 2026
Non-Final Rejection mailed — §102, §103
Apr 20, 2026
Response Filed
May 07, 2026
Non-Final Rejection mailed — §102, §103
Sep 04, 2026
Response Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740048
SEMICONDUCTOR MEMORY DEVICE INCLUDING BURIED GATE PATTERN
3y 11m to grant Granted Sep 15, 2026
Patent 12696826
SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR DEVICES
3y 8m to grant Granted Jul 28, 2026
Patent 12652804
FABRICATION METHOD FOR A THREE-DIMENSIONAL MEMORY ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL
2y 8m to grant Granted Jun 09, 2026
Patent 12648457
FACE-TO-FACE DIES WITH A VOID FOR ENHANCED INDUCTOR PERFORMANCE
3y 2m to grant Granted Jun 02, 2026
Patent 12642063
SEMICONDUCTOR DEVICE INCLUDING ISOLATION STRUCTURE WITH IMPURITY AND METHOD FOR MANUFACTURING THE SAME
3y 1m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+17.9%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 221 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month