Prosecution Insights
Last updated: May 29, 2026
Application No. 18/514,126

Chamfered Die of Semiconductor Package and Method for Forming the Same

Non-Final OA §102§103
Filed
Nov 20, 2023
Priority
Jan 29, 2020 — provisional 62/967,245 +2 more
Examiner
ANDERSON, WILLIAM H
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
4 (Non-Final)
86%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
174 granted / 203 resolved
+17.7% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
249
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
78.1%
+38.1% vs TC avg
§102
8.8%
-31.2% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 203 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 15-16 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai (US 20200105641 A1). The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding independent claim 15, Lai discloses a method of manufacturing a semiconductor device (Fig. 9C), the method comprising: forming a first die (110, See annotated figure) with a chamfered first corner (at 170), a second die (110, See annotated figure) with a chamfered first corner (at 170), a third die (110, See annotated figure) with a chamfered first corner (at 170), and a fourth die (110, See annotated figure) with a chamfered first corner (at 170); encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant (Fig. 1A: 130), wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view (these four corners meet at the same junction J, thus forming a region that can be designated as a quadrilateral shape within the breadth of the claim), the encapsulant filling the quadrilateral shape region (Fig. 1A: 130; [0022]: “After that, an encapsulant 130 is formed to encapsulate the dies 110”); forming a redistribution structure (Fig. 9C: 140; [0023]: “The redistribution structure 140 is formed”) on the encapsulant, the first die, the second die, the third die, and the fourth die; and after forming the redistribution structure on the encapsulant, the first die, the second die, the third die, and the fourth die, removing a material from the redistribution structure (Fig. 9B: hole 170 has removed a portion of RDL 140) and a material from the encapsulant (Fig. 9B: hole 170 has removed a portion of encapsulant 130) to form a hole (170) extending through the redistribution structure and the encapsulant, the hole being disposed in the quadrilateral shape region. Illustrated below is a marked and annotated figure of Fig. 9C of Lai. PNG media_image1.png 501 502 media_image1.png Greyscale Regarding claim 16, Lai discloses the method of claim 15 (Fig. 9C), wherein the chamfered first corner of the first die comprises a linear edge (a vertically extending edge, extending out of the page) in the top-down view (Fig. 9C shows a horizontal cross-section of this edge). Regarding claim 18, Lai discloses the method of claim 15 (Fig. 9C), wherein the first die further comprises a chamfered second corner, a chamfered third corner, and a chamfered fourth corner (all four corners are chambered). Regarding claim 19, Lai discloses the method of claim 15 (Fig. 9C), further comprising: inserting a bolt (200) through the hole, wherein the bolt overlaps (horizontally overlaps) a first space occupied by a first corner of the first die prior to chamfering the first corner of the first die to form the chamfered first corner of the first die (the corner is chamfered in the method sequence from Fig. 9B to 9C in order to enable including bolt 200). Regarding claim 20, Lai discloses the method of claim 19 (Fig. 9C), wherein the bolt further overlaps (horizontally overlaps) a second space occupied by a first corner of the second die prior to chamfering the first corner of the second die to form the chamfered first corner of the second die (the corner is chamfered in the method sequence from Fig. 9B to 9C in order to enable including bolt 200). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claims 1, 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 10096578 B1) in view of Tai (US 20210118806 A1) and Kurose (US 20190057874 A1) Regarding claim 1, Yeh discloses a method of manufacturing a semiconductor device (Fig. 4B), the method comprising: forming a die (43) comprising an insulating layer over a semiconductor substrate (col. 4, lines 51-67: “a semiconductor device (e.g. a die)”), wherein the die has a shape of an octagon in a top-down view (selecting the Fig. 1D: die 13 embodiment (a partial perspective view). Note: the shape of top surface 132 is octagonal, as shown in top-down view in Fig. 1B), and wherein the die has a chamfered corner (surface 135) with a linear edge (See annotated Fig. 1D for edge designation) in a plan view; applying an encapsulant (14) around the die (at least partially around, as applied in Fig. 4B to die 43); and forming a redistribution structure (10. Note: the inclusion of a redistribution structure is relied upon here. The method sequence “forming a redistribution structure over…” is discussed below) over the chamfered corner of the die and over the encapsulant (vertically over. See annotated Fig. 4B for direction designation), wherein in a cross-sectional view, a portion of the encapsulant fills (See annotated Fig. 4B) a space (See annotated Fig. 4B) that vertically overlaps the die, wherein the space that vertically overlaps the die extends continuously from a beveled sidewall of the chamfered corner in the insulating layer to a bottom surface of the redistribution structure along a line (See dashed reference line in annotated figure) perpendicular to a top surface of the die. Illustrated below are marked and annotated figures of Figs. 4B and 1D of Yeh. PNG media_image2.png 330 627 media_image2.png Greyscale PNG media_image3.png 484 556 media_image3.png Greyscale Yeh generally discloses the spatial configuration of the redistribution structure with respect to other structures within the device (col. 3, lines 13-22: “disposed”), however is silent on how the step of forming the redistribution structure is achieved. Thus, Yeh fails to teach “forming a redistribution structure over the chamfered corner of the die and over the encapsulant”. Tai discloses a method in the same field of endeavor including a die (Fig. 4J: 13), an encapsulant (16), and a redistribution structure (10). Tai further teaches the method of including the redistribution structure may be designed two ways: 1) forming the redistribution structure over the die and the encapsulant (the embodiment of Figs. 4C-4G); or 2) applying the die and the encapsulant to the redistribution structure (the embodiment of Figs. 7E-7G). Since Yeh and Tai both teach methods including redistribution structures, a person having ordinary skill in the art before the effective filing date would have readily recognized the finite number of predictable solutions for assembling the die, encapsulant, and redistribution structure (of Tai) would have predictable results when used in the same situation (of Yeh). Absent unexpected results, it would have been obvious to try using a different method of assembling the die, encapsulant, and redistribution structure. Thus, the claim would have been obvious to a person of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2141.03 (I), MPEP 2143 (1)(E). Yeh generally discloses forming the die (Fig. 1D: die 13; col. 3, lines 13-22: “the electronic component…such as…”), however is silent regarding specific method of forming this die. Thus, Yeh in view of Tai fails to teach “forming a die comprising an insulating layer over a semiconductor substrate,” and “wherein the space that vertically overlaps the die extends continuously from a beveled sidewall of the chamfered corner in the insulating layer to a bottom surface of the redistribution structure along a line perpendicular to a top surface of the die”. Kurose discloses a method: forming a die (Fig. 10) comprising an insulating layer (selecting the embodiment of Fig. 11: insulating layer 100) over a semiconductor substrate (102; [0075]: “wafer” in combination with [0052]: “wafer…silicon”), wherein the die has a shape of an octagon in a top-down view (Fig. 6: die 44 has an octagon shape), and wherein the die has a chamfered corner (See annotated Fig. 6) with a linear edge (See annotated Fig. 6) in a plan view; applying an encapsulant around the die; and forming a redistribution structure over the chamfered corner of the die and over the encapsulant, wherein in a cross-sectional view, a portion of the encapsulant fills a space that vertically overlaps the die, wherein the space that vertically overlaps the die extends continuously from a beveled sidewall of the chamfered corner in the insulating layer (The chamfered corner encompasses the entire sidewall of the die, because Kurose teaches: 1) the die has the chamfered corner in Fig. 6; and 2) the shape of the die is formed by the insulating layer in Fig. 11.) to a bottom surface of the redistribution structure along a line perpendicular to a top surface of the die. Modifying the method of Yeh in view of Tai by forming the die comprising the method steps of Kurose would arrive at the claimed method and insulating layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the die is a chamfered die (Yeh: Fig. 1D: die 13; Kurose: Fig. 6: die 44). Kurose provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed method and insulating layer configuration because it would reduce manufacturing damage, by reducing chips and cracks during formation of the die ([0049]: “the sides of the die will have no chips or cracks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and insulating layer configuration because it would reduce manufacturing damage. Illustrated below is a marked and annotated figure of Fig. 6, and Fig. 11 of Kurose. PNG media_image4.png 340 376 media_image4.png Greyscale PNG media_image5.png 245 545 media_image5.png Greyscale Regarding claim 3, Yeh in view of Tai and Kurose discloses the method of claim 1, wherein forming the die comprises chamfering a corner of the die using a laser saw to form the chamfered corner (Kurose: [0066]: “a laser”). Regarding claim 7, Yeh in view of Tai and Kurose discloses the method of claim 1 (Kurose: Fig. 11), wherein an angle θ between a bottom of the die and a facet of the chamfered corner of the die is in a range of 30° to 90° (the angle formed by the notch 106 appears to form a 90º angle). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Tai and Kurose as applied to claim 1 above, and further in view of Loo (US 5648890 A). Regarding claim 2, Yeh in view of Tai and Kurose discloses the method of claim 1 (Yeh: Fig. 4B), however, fails to teach the method “further comprising inserting a bolt through the redistribution structure and the encapsulant, wherein the bolt is adjacent to the chamfered corner”. Loo discloses a method where heat dissipation is a design consideration during the manufacturing process (col. 5, lines 28-36: “heat sink”) and further discloses the method further comprising inserting a bolt (530) through the redistribution structure (514) and the lateral enclosure (516), wherein the bolt is adjacent to the die corner (any of innermost corners of any of 12). The method of Loo is related to the method of Yeh because: 1) Yeh also discloses heat dissipation from the device is a design consideration during the manufacturing process (col. 7, line 56-col. 8, line 3: “heat dissipation”); and 2) the encapsulant of Yeh performs at least the function of laterally enclosing the die and external connectors thereof (as shown in Fig. 4B, where 43 is electrically connected to 10). Therefore, modifying the method of Yeh in view of Tai and Kurose by including a bolt in the same way as Loo, would arrive at the claimed method, further comprising inserting a bolt through the redistribution structure (of Yeh) and the encapsulant (of Yeh), wherein the bolt is adjacent to the chamfered corner (of Yeh). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because, in both cases heat dissipation is a design consideration of laterally enclosed dies. Loo provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include a bolt in that it would enable affixing a thermal module to the device, thereby improving heat dissipation (col. 6, lines 56-67: 520, “heat sink…depending on the amount of heat generated”). Therefore, the claimed bolt configuration within the method would have been obvious to one of ordinary skill in the art before the effective filing date because it would enable improved heat dissipation. MPEP 2143 (I)(G). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh, Tai, and Kurose as applied to claim 3 above, and further in view of Pirogovsky (US 20100248451 A1). Regarding claim 4, Yeh in view of Tai and Kurose discloses the method of claim 3 (Kurose: Fig. 11), however fails to teach specific settings for the laser saw. Thus, Yeh, Tai, and Kurose fail to teach “wherein the laser saw performs the chamfering of the corner with a wavelength in a range of 490 nm to 570 nm and a power in a range of 10 W to 20 W”. Pirogovsky teaches a method chamfering a corner of a die using a laser saw (Fig. 7a: 104), wherein the laser saw performs the chamfering of the corner with a wavelength in a range of 490 nm to 570 nm ([0033]: 532 nm) and a power in a range of 10 W to 20 W ([0033]: 20 W). The method of Pirogovsky is related to the method of Yeh, Tai, and Kurose because Pirogovsky teaches the method may be used to produce varied chamfer shapes (“kerfs…straight lines…curves…other shapes” [0038]). Therefore, a person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating the laser settings and techniques of Pirogovsky to produce the chamfered shape of Yeh, Tai, and Kurose. Pirogovsky provides a teaching that would motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed laser settings and techniques, because the technique would waste less material (Pirogovsky: [0008]: “reduce the substrate area”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have a method with the claimed laser configuration because it would waste less material. MPEP 2143 (I)(G). Illustrated below is Fig. 7a of Pirogovsky. PNG media_image6.png 410 331 media_image6.png Greyscale Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh, Tai, and Kurose as applied to claim 1 above, and further in view of Liu (US 9837366 B1). Regarding claim 5, Yeh in view of Tai and Kurose discloses the method of claim 1 (Yeh: Fig. 4B), however fails to teach “the die comprises a seal ring in the insulating layer, and wherein the linear edge of the chamfered corner is parallel to a linear edge of the seal ring in the top-down view”. Liu discloses a method with a die (Fig. 3I: 310), wherein the die comprises a seal ring (326) in the insulating layer (320), and wherein the linear edge of the chamfered corner is parallel to a linear edge of the seal ring in the top-down view (Fig. 5: linear edges at corners of 162). Modifying the method of Yeh, Tai, and Kurose, by having the die (of Yeh/Tai/Kurose) comprises a seal ring in the top-down view having a shape of an octagon (of Liu) would provide an octagonal seal ring configured among an octagonal die surface (of Yeh/Tai/Kurose), and thus arrive at the claimed seal ring configuration “wherein the die comprises a seal ring in the insulating layer, and wherein the linear edge of the chamfered corner is parallel to a linear edge of the seal ring in the top-down view”. Liu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the seal ring in the method because it would protect the device during manufacture, thereby enhancing manufacturing yield (col. 4, line 64-col. 5, line 23: “can stop undesirable damaging”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Liu does not teach the inclusion of the seal ring having any special requirements or changes to the die to enable the inclusion. Therefore, the claimed seal ring configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it would protect the device from manufacturing defects, thereby enhancing manufacturing yield. MPEP 2143 (I)(G). Claims 8-9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kurose and Liu. Regarding independent claim 8, Lai discloses a method of manufacturing a semiconductor device (Fig. 9C), the method comprising: forming a first die (110, See annotated figure), wherein forming the first die comprises chamfering a first corner of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view; encapsulating the first die with an encapsulant (Fig. 1A: 130); and forming a redistribution structure over the encapsulant and the first die (Fig. 9C: 140; [0023]: “The redistribution structure 140 is formed”), wherein forming the redistribution structure comprises forming layers of metallization patterns and dielectric layers therebetween ([0023]: “the dielectric layer 142 is a multiple-layered or single-layered structure. In some embodiments, the redistribution conductive patterns 144 include a plurality of conductive layers”); and after forming the redistribution structure over the encapsulant and the first die, removing a material from the redistribution structure (Fig. 9B: hole 170 has removed a portion of RDL 140) and a material from the encapsulant (Fig. 9B: hole 170 has removed a portion of encapsulant 130) to form a hole (170) through the redistribution structure and the encapsulant, the hole being adjacent the chamfered first corner of the first die in a plan view. Lai fails to teach “wherein forming the first die comprises chamfering a first corner of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate and a seal ring, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view;” and “the hole being adjacent the chamfered first corner of the first die in a plan view”. Kurose discloses a method of manufacturing a semiconductor device, the method comprising: forming a first die (Fig. 6: die 44), wherein forming the first die comprises chamfering a first corner (See annotated Fig. 6 for corner designation) of the first die to form a chamfered first corner of the first die, wherein the first die comprises a semiconductor substrate (selecting the embodiment of Fig. 11: insulating layer 100;(102; [0075]: “wafer” in combination with [0052]: “wafer…silicon”) Modifying the method of Lai by forming the first die in the way disclosed by Kurose would arrive at the claimed method and chamfered first corner configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the die is a semiconductor die (Lai: Fig. 9C: die 110; Kurose: Fig. 6: die 44). Kurose provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed die formation method because it would reduce manufacturing damage, by reducing chips and cracks during formation of the die ([0049]: “the sides of the die will have no chips or cracks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and insulating layer configuration because it would reduce manufacturing damage. MPEP 2143 (I)(G). Lai in view of Kurose fails to teach “wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view”. Liu a method wherein the first die (Fig. 3I: 310) comprises a semiconductor substrate and a seal ring (326) over the semiconductor substrate (310), and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view (Fig. 5: linear edges at corners of 162). Modifying the method of Lai and Kurose by having the first die (of Lai/Kurose) comprise a seal ring (of Liu) over the semiconductor substrate would provide an octagonal seal ring configured among an octagonal die surface (of Lai/Kurose), and thus arrive at the claimed seal ring configuration “wherein the first die comprises a semiconductor substrate and a seal ring over the semiconductor substrate, and wherein an edge of the chamfered first corner is parallel to an edge of the seal ring in a top down view”. Liu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the seal ring in the method because it would protect the device during manufacture, thereby enhancing manufacturing yield (col. 4, line 64-col. 5, line 23: “can stop undesirable damaging”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Liu does not teach the inclusion of the seal ring having any special requirements or changes to the die to enable the inclusion. Therefore, the claimed seal ring configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it would protect the device from manufacturing defects, thereby enhancing manufacturing yield. MPEP 2143 (I)(G). Regarding claim 9, Lai in view of Kurose and Liu discloses the method of claim 8, wherein chamfering the first corner of the first die comprises using a laser saw (Kurose: [0066]: “a laser”). Regarding claim 11, Lai in view of Kurose and Liu discloses the method of claim 8 (Kurose: Fig. 11), wherein chamfering the first corner of the first die comprises forming a rectangular chamfered surface (the chamfer formed by groove 104 appears substantially vertical, therefore the resultant shape of the die in Fig. 6 would be a substantially vertical rectangle). Regarding claim 12, Lai in view of Kurose and Liu discloses the method of claim 8 (Kurose: Fig. 11), wherein chamfering the first corner of the first die comprises forming a trapezoidal chamfered surface (the chamfer formed by groove 104 appears substantially vertical, therefore the resultant shape of the die in Fig. 6 would be a substantially vertical rectangle. Note: the plain and ordinary meaning of trapezoid, consistent with the inclusive definition, i.e., a quadrilateral having at least one pair of parallel sides; thus the rectangular chamfered surface is a trapezoid). Regarding claim 13, Lai in view of Kurose and Liu discloses the method of claim 8, wherein the seal ring is disposed in an insulating layer (Liu: Fig. 3I: 330) over the semiconductor substrate (310), wherein the seal ring further extends into an interconnect structure (320) that is disposed between the insulating layer and the semiconductor substrate (sandwiched between), wherein chamfering the first corner of the first die comprises forming a first chamfered surface (330 at 312) and a second chamfered surface (320 at 312) abutting the first chamfered surface (vertically abutting), wherein the first chamfered surface is a surface of the insulating layer (this is the selected surface shown in Fig. 3I), and wherein the second chamfered surface is a surface of the interconnect structure (this is the selected surface shown in Fig. 3I). Regarding claim 14, Lai in view of Kurose and Liu discloses the method of claim 8 (Lai: Fig. 8C), further comprising attaching a thermal module (190) to the redistribution structure with a bolt (200), the thermal module being on a back side of the first die opposite the redistribution structure (module 190 and RDL 140 are on opposing sides of die 110), the bolt extending through the hole (fully through the hole). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lai, Kurose, and Liu as applied to claim 8 above, and further in view of Yeh. Regarding claim 10, Lai in view of Kurose and Liu teaches the method of claim 8, but fails to teach “wherein chamfering the first corner of the first die comprises forming a triangular chamfered surface”. Yeh teaches chamfering the first corner of the first die (Fig. 1C: corner of die 13) comprises forming a triangular chamfered surface (surface 136). Modifying the method of Lai, Kurose, and Liu by including the additional chamfering technique of Yeh would arrive at the claimed chamfering method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the first die is an encapsulated semiconductor die (Yeh: Fig. 1C: encapsulant 14 on die 13; Lai: Fig. 8C: encapsulant 130 on die 110). Yeh provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the additional chamfering technique in that it would prevent the device from cracking by relieving stress in the device (col. 4, lines 51-67: “can provide for a release or redistribution of stress in the package body”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chamfering method configuration because it would relieve stress in the device. MPEP 2143 (I)(G). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lai as applied to claim 15 above, and further in view of Yeh. Regarding claim 17, Lai discloses the method of claim 15, but fails to teach “wherein the chamfered first corner of the first die comprises an inverted corner in the top-down view”. Yeh teaches chamfering the first corner of the first die (Fig. 1C: corner of die 13) wherein the chamfered first corner of the first die comprises an inverted corner in the top-down view (surfaces 135/136 intersect at an inverted corner, and this intersection is visible in top-down view). Modifying the method of Lai by including the additional chamfering technique of Yeh would arrive at the claimed chamfering method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the first die is an encapsulated semiconductor die (Yeh: Fig. 1C: encapsulant 14 on die 13; Lai: Fig. 8C: encapsulant 130 on die 110). Yeh provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the additional chamfering technique in that it would prevent the device from cracking by relieving stress in the device (col. 4, lines 51-67: “can provide for a release or redistribution of stress in the package body”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chamfering method configuration because it would relieve stress in the device. MPEP 2143 (I)(G). Claims Regarding independent claim 15, Lai discloses a method of manufacturing a semiconductor device (Fig. 9C), the method comprising: forming a first die (110, See annotated figure) with a chamfered first corner (at 170), a second die (110, See annotated figure) with a chamfered first corner (at 170), a third die (110, See annotated figure) with a chamfered first corner (at 170), and a fourth die (110, See annotated figure) with a chamfered first corner (at 170); encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant (Fig. 1A: 130), wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view (these four corners meet at the same junction J, thus forming a region that can be designated as a quadrilateral shape within the breadth of the claim), the encapsulant filling the quadrilateral shape region (Fig. 1A: 130; [0022]: “After that, an encapsulant 130 is formed to encapsulate the dies 110”); forming a redistribution structure (Fig. 9C: 140; [0023]: “The redistribution structure 140 is formed”) on the encapsulant, the first die, the second die, the third die, and the fourth die; and after forming the redistribution structure on the encapsulant, the first die, the second die, the third die, and the fourth die, removing a material from the redistribution structure (Fig. 9B: hole 170 has removed a portion of RDL 140) and a material from the encapsulant (Fig. 9B: hole 170 has removed a portion of encapsulant 130) to form a hole (170) extending through the redistribution structure and the encapsulant, the hole being disposed in the quadrilateral shape region. Lai fails to teach the method “forming a first die with a chamfered first corner, a second die with a chamfered first corner, a third die with a chamfered first corner, and a fourth die with a chamfered first corner; encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant, wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view”. 15. (Previously presented) A method of manufacturing a semiconductor device, the method comprising: forming a first die with a chamfered first corner, a second die with a chamfered first corner, a third die with a chamfered first corner, and a fourth die with a chamfered first corner; encapsulating the first die, the second die, the third die, and the fourth die with an encapsulant, wherein the chamfered first corner of the first die, the chamfered first corner of the second die, the chamfered first corner of the third die, and the chamfered first corner of the fourth die form a quadrilateral shape region in a top-down view, the encapsulant filling the quadrilateral shape region; forming a redistribution structure on the encapsulant, the first die, the second die, the third die, and the fourth die; and after forming the redistribution structure on the encapsulant, the first die, the second die, the third die, and the fourth die, removing a material from the redistribution structure and a material from the encapsulant to form a hole extending through the redistribution structure and the encapsulant, the hole being disposed in the quadrilateral shape region. Allowable Subject Matter Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the allowable subject matter of claim 21 is the inclusion of the limitation “wherein the beveled sidewall of the chamfered corner directly contacts the bottom surface of the redistribution structure in the cross-sectional view” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “beveled sidewall of the chamfered corner”, “directly contacts”, and “redistribution structure” in combination with the “encapsulant” and “space” configurations of claim 1 all other limitations in claims 21 and 1. Electrical connectors were found in the prior art that would enable the claimed “direct contact” configuration. However, these features were not found capable of reasonably rendering obvious the claim when considered as a whole because the direct contact was not disclosed in a way teaching or reasonably suggesting the claimed encapsulant and space configurations. Response to Arguments Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive. Applicant argues: Applicant argues with respect to amended claim 1 that “Yeh fails to even disclose an insulating layer with a chamfered surface in the context of claim 1”. Remarks at pg. 9. Examiner’s reply: Applicant’s arguments, see pg. 9, filed 4/20/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. More specifically, Applicant argues with respect to amended claim 1 that the claimed chamfering configuration of the insulating layer differs from the chamfering configuration of Yeh. The examiner agrees because although Yeh teaches chamfering the die; Yeh makes no specific teachings regarding the chamfering in relation to the insulating layer. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kurose. Applicant states: Applicant provides a statement (pg. 10) pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference (Chun, US 20200211922 A1) and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Examiner’s reply: The examiner finds the statement establishing an exception for the Chun reference. Accordingly, the rejections based on Chun alone, or combinations with Chun have been withdrawn. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lai (US 20200243429 A1) discloses “after forming the redistribution structure (112) over the encapsulant (110) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 9) to form a hole (144) through the redistribution structure and the encapsulant”. Yu (US 20200411488 A1) discloses “after forming the redistribution structure (86) over the encapsulant (80) and the first die (66), removing a material from the redistribution structure and a material from the encapsulant (Fig. 21) to form a hole (98) through the redistribution structure and the encapsulant”. Huang (US 20210125960 A1) discloses “after forming the redistribution structure (170) over the encapsulant (150) and the first die (130), removing a material from the redistribution structure and a material from the encapsulant (Fig. 1D) to form a hole (190) through the redistribution structure and the encapsulant”. Lai (US 20200212018 A1) discloses “after forming the redistribution structure (430) over the encapsulant (406) and the first die (405), removing a material from the redistribution structure and a material from the encapsulant (28) to form a hole (442) through the redistribution structure and the encapsulant”. Chun (US 20200395257 A1) discloses “after forming the redistribution structure (108) over the encapsulant (106) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 13) to form a hole (148) through the redistribution structure and the encapsulant”. Chun (US 20200185304 A1) discloses “after forming the redistribution structure (108) over the encapsulant (106) and the first die (50), removing a material from the redistribution structure and a material from the encapsulant (Fig. 12) to form a hole (148) through the redistribution structure and the encapsulant”. Yu (US 20200006252 A1) discloses “after forming the redistribution structure (56) over the encapsulant (38) and the first die (26), removing a material from the redistribution structure and a material from the encapsulant (Fig. 9) to form a hole (the hole for bolt 69) through the redistribution structure and the encapsulant”. Lai (US 20200243494 A1) discloses “after forming the redistribution structure (110) over the encapsulant (106) and the first die (102), removing a material from the redistribution structure and a material from the encapsulant (Fig. 11C) to form a hole (160) through the redistribution structure and the encapsulant”. Yu (US 20200203301 A1) discloses “after forming the redistribution structure (110) over the encapsulant (108) and the first die (106A), removing a material from the redistribution structure and a material from the encapsulant (Fig. 5) to form a hole (TH) through the redistribution structure and the encapsulant”. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Show 2 earlier events
Jul 07, 2025
Response Filed
Jul 24, 2025
Final Rejection mailed — §102, §103
Sep 24, 2025
Response after Non-Final Action
Nov 24, 2025
Request for Continued Examination
Nov 29, 2025
Response after Non-Final Action
Jan 20, 2026
Non-Final Rejection mailed — §102, §103
Apr 20, 2026
Response Filed
May 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642063
SEMICONDUCTOR DEVICE INCLUDING ISOLATION STRUCTURE WITH IMPURITY AND METHOD FOR MANUFACTURING THE SAME
3y 1m to grant Granted May 26, 2026
Patent 12635575
SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS, AND CHIPS FOR SUCH A STACK
3y 1m to grant Granted May 19, 2026
Patent 12610516
Semiconductor Structure and Method Making the Same
3y 2m to grant Granted Apr 21, 2026
Patent 12568648
BACKSIDE SOURCE/DRAIN CONTACTS AND METHODS OF FORMING THE SAME
4y 2m to grant Granted Mar 03, 2026
Patent 12564081
ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE WITH WIRING GROUPS FOR PARALLEL SIGNAL TRANSMISSION
3y 2m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+15.4%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 203 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month