Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 35044-0158C1
Filling Date: 11/20/23
Inventor: Chang et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species III, claims 1-20 in the reply filed on 01/27/26 is acknowledged. The traversal is on the ground(s) that top and cross-sectional view are a same embodiment. This is found persuasive. This office action will examine claims 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13-19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al (US 2022/0302085 A1).
Regarding claim 1, Chang discloses a die (Fig. 1) comprising: a semiconductor substrate 102 (Para. 33); an interconnect structure 104, 110 (Paras. 20, 67) disposed on a front side of the semiconductor substrate 102; a through-substrate via (TSV) structure 162 (Paras. 32, 34) extending through the semiconductor substrate 102; and a fuse structure 180 (Para. 34) electrically connecting the TSV structure 162 and the interconnect structure 104, 110, the fuse structure 180 comprising a resistance control layer 182 (Para. 35) having a higher electrical resistance (Para. 35) than at least one of the interconnect structure 104, 110 and the TSV structure 162.
Regarding claim 13, Chang discloses a semiconductor package (Figures 1-4) comprising: a first die 100 (Para. 25) comprising: a first semiconductor substrate 102 (Paras. 18, 33); a first dielectric structure 104 comprising a substrate oxide layer 104A (Para. 20) disposed directly on a front side of the first semiconductor substrate 102 and inter-layer dielectric (ILD) layers 104B-104G (Para. 20) disposed on the substrate oxide layer 104A; a first interconnect structure 106 (Paras. 24, 27) embedded in the first dielectric structure 104; a first through-substrate via (TSV) structure 162 (Para. 34) extending through the first semiconductor substrate 102; and a first fuse structure 180 (Para. 34) electrically connecting the first TSV structure 162 to the first interconnect structure 106, the first fuse structure 180 comprising pillars 186 (Para. 37) embedded in the substrate oxide layer 104A and electrically connected to the first interconnect structure 106; and a second die 200 (Para. 51) disposed on the first die 100 and electrically connected to the first TSV structure 162.
Regarding claim 14, Chang further discloses the semiconductor package of claim 13, wherein the first fuse structure 180 further comprises a resistance control layer 182 (Para. 35) that electrically connects the pillars 186 and the first TSV structure 162.
Regarding claim 15, Chang further discloses the semiconductor package of claim 14, wherein: an interface between the first TSV structure 162 and a first surface of the resistance control layer 182 has a first surface area; an interface between the pillars 186 and an opposing second surface of the resistance control layer 182 has a second surface area; and the first surface area is at least ten times greater than the second surface area (Para. 39).
Regarding claim 16, Chang further discloses the semiconductor package of claim 14, wherein the pillars 186 have a higher electrical resistance (because it is connected to resistance layer 182 directly, width is small) than at least one of the first interconnect structure 106 and the first TSV structure 162.
Regarding claim 17, Chang further discloses the semiconductor package of claim 13, wherein the second die 200 comprises: a second semiconductor substrate 65 (Para. 57); a second dielectric structure 204 (top one) comprising a substrate oxide layer 204 (bottom most layer) disposed directly on a front side of the second semiconductor substrate 65 and inter-layer dielectric (ILD) layers 204 (top few layers) disposed on the substrate oxide layer 204 (bottom most layer); a second interconnect structure embedded in the second dielectric structure 204; a second through-substrate via (TSV) structure 67 (portion inside 65) extending through the second semiconductor substrate 65; and a second fuse structure 280 (Para. 61) embedded in the substrate oxide layer 204 of the second die 200 and electrically connecting the second TSV structure 67 to the second interconnect structure 200.
Regarding claim 18, Chang discloses a die (Figs. 1, 4) comprising: a semiconductor substrate 102 (Para. 66); an interconnect structure 204 (Para. 20) disposed on a front side of the semiconductor substrate 102; a through-substrate via (TSV) structure 162 (Paras. 32, 34) extending through the semiconductor substrate 102; and a fuse structure 180 (Para. 34) disposed between and electrically connecting the TSV structure 162 and the interconnect structure 104, the fuse structure 180 comprising: pillars 186 (Para. 37) electrically connected to the interconnect structure 104; and a resistance control layer 182 (Para. 35) electrically connecting the TSV structure 162 and the pillars 186, wherein the resistance control layer 182 has a higher electrical resistance 182 (it has resistance, Para. 67) than at least one of the interconnect structure 104 and the TSV structure 167.
Regarding claim 19, Chang further discloses the die of claim 18, further comprising: a barrier layer (Para. 33) disposed between the TSV structure 162 and the semiconductor substrate 102; and a die bonding pad 65 (Para. 57) disposed on a back side of the first semiconductor substrate 102 and electrically connected to the first TSV structure 162 (portion inside 102),wherein the TSV structure 162 comprises a seed layer and a TSV material layer disposed inside of the seed layer (Para. 49).
Regarding claim 20, Chang further discloses the die of claim 18, further comprising a contact etch stop layer (CESL) 184 (Para. 36) disposed on the resistance control layer 182.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable Lin et al (US 2017/0011988 A1) in view of Chang et al (US 2022/0302085 A1).
Regarding claim 1, Lin discloses a die (Figures 1-16, specifically Fig. 11) comprising: a semiconductor substrate 10 (Para. 9); an interconnect structure 20 (Para. 12) disposed on a front side of the semiconductor substrate 10; a through-substrate via (TSV) structure 18 (Para. 12) extending through the semiconductor substrate 10; and a fuse structure 12 (Para. 9) electrically connecting the TSV structure 18 and the interconnect structure 20, the fuse structure having a higher electrical resistance than at least one of the interconnect structure 20 (22T is metal, Para. 12) and the TSV structure 18.
Lin does not explicitly disclose the fuse structure comprising a resistance control layer.
However, Chang discloses the fuse structure comprising a resistance control layer (this is inherent for the fuse, Para.34)
Chang teaches the above modification is used to control resistance of the device 182 (Fig. 1, Para. 34). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Lin fuse with Chang fuse including resistance control layer as suggested above to control resistance of the device (Para. 34).
Regarding claim 2, Lin further discloses the die of claim 1, wherein the fuse structure further comprises a contact structure 14 (Para. 11) that electrically connects the interconnect structure 20 and the resistance control layer 12.
Regarding claim 3, Chang further discloses the die of claim 2, wherein: an interface between the TSV structure 162 (Figs. 1, 4, Para. 32) and a first surface of the resistance control layer 182 has a first surface area; an interface between the contact structure 186 (Para. 37) and an opposing second surface of the resistance control layer 182 has a second surface area; and the first surface area (between 162 and 182) is greater than the second surface area (between 182 and 186).
Regarding claim 4, Chang further discloses the die of claim 3, wherein the first surface area is at least ten times greater than the second surface area (Para. 67).
Regarding claim 5, Lin further discloses the die of claim 1, wherein the resistance control layer 12 has a higher electrical resistance (inherent) than both the first interconnect structure 20, 22T (metal) and the first TSV structure 18.
Regarding claim 6, Lin further discloses the die of claim 5, wherein: the TSV structure 18 comprises copper (Para. 10), a copper alloy, aluminum, an aluminum alloy, silver, or a combination thereof.
Lin does not explicitly disclose the interconnect structure comprises copper, a copper alloy, aluminum, an aluminum alloy, silver, or a combination thereof.
However, Lin discloses the interconnect structure is metal 22T (Para. 12) and connection element is Cu (Para. 26). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the interconnect structure comprises copper for low resistance as it is common in the art.
Chang further discloses the resistance control layer comprises silicon-germanium, tungsten 182 (Fig. 1, Para. 35), titanium nitride, tantalum nitride, or a combination thereof.
Regarding claim 7, Lin further discloses the die of claim 5, wherein: the interconnect structure 22T and the TSV structure 18 comprise at least 90% Cu (Paras. 12, 26, obvious); and the resistance control layer 182 comprises silicon germanium, tungsten (Para. 35), titanium nitride, tantalum nitride, or a combination thereof.
Regarding claim 8, Chang further discloses the die of claim 2, wherein the contact structure 186 comprises at least one pillar that extends between a metal line 106 (Para. 27) of the interconnect structure 106 and the resistance control layer 182.
Regarding claim 9, Chang further discloses the die of claim 2, wherein the fuse structure 180 (Para. 34) further comprises a contact etch stop layer (CESL) 184 (Para. 36) disposed on the second surface of the resistance control layer 182.
Regarding claim 10, Chang further discloses the die of claim 2, wherein the CESL comprises a single layer or multiple layers of an etch-stop material comprising silicon nitride, silicon carbide, silicon carbon nitride 184 (Para. 36), a combination thereof.
Regarding claim 11, Chang further discloses the die of claim 2, wherein the fuse structure 180 further comprises a barrier layer (Para. 24) disposed between the TSV structure 162 and the semiconductor substrate 102.
Regarding claim 12, Chang further discloses the die of claim 2, further comprising a dielectric structure comprising a substrate oxide layer (SOI substrate) disposed directly on the front side of the semiconductor substrate 102 and inter-layer dielectric (ILD) layers 104 (Para. 20) disposed on the substrate oxide layer, wherein: the first interconnect structure 106 is embedded in the ILD layers 104; and the fuse structure 180 is embedded in the substrate oxide layer 102, between the first TSV structure and the interconnect structure 106.
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817