DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/514,356 filed on 08/27/2021. Claims 1-20 are pending in the office action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations “a first plurality of base layout cells in a layout, wherein the first plurality of base layout cells are identical, and a second plurality of base layout cells in the layout, wherein the second plurality of base layout cells are identical to the first plurality of base layout cells, and wherein each of the second plurality of base layout cells is flipped with respect to the first plurality of base layout cells” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 14, and 20 are objected to because of the following informalities:
Per claim 2: replaces “an NAND” with -- a NAND --.
Per claim 14: replaces “an NAND” with -- a NAND --.
Per claim 20: replaces “an NAND” with -- a NAND --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 16: recited “a first plurality of base layout cells in a layout, wherein the first plurality of base layout cells are identical, and a second plurality of base layout cells in the layout, wherein the second plurality of base layout cells are identical to the first plurality of base layout cells” appear “a first plurality of base layout cells” and “a second plurality of base layout cells” in a same layout, but unclear whether they are in the same circuit, because the application’s specification and figures 4A-4B describes different modification (i.e., flipping, rotating, mirror) and figure 6 appears random and/or regular abut arrangement. Neither Application specification nor drawings describes “a first plurality of base layout cells” are laid out in the same circuit, likewise, “a second plurality of base layout cells”.
For the broadest interpretation, “a first plurality of base layout cells” and “a second plurality of base layout cells”, where each of base layout cell of a first/second plurality of base layout cells is arranged (abut) in a layout, but not necessary in the same circuit or component as figure 6.
Claims 17-20 are also rejected because are depended directly or indirectly from claim 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., (U.S. Pub. 2020/0136840).
As per claim 16: Lee discloses a method, comprising:
placing a first plurality of base layout cells in a layout, wherein the first plurality of base layout cells are identical, and wherein each of the first plurality of base layout cells comprises a pattern representing source/drain (S/D) contacts of the plurality of transistors (‘840, fig. 2A, cell layout 200A, contact pattern 208a-208n, 209, 242, par. [0083] [0084], fig. 8A-10, cells type 1A (first base layout cells), fig. 11, a first set of layout design of a first set of PUF cells 1102, par. [0073] source/drain of transistors);
placing a second plurality of base layout cells in the layout, wherein the second plurality of base layout cells are identical to the first plurality of base layout cells, and wherein each of the second plurality of base layout cells is flipped with respect to the first plurality of base layout cells (‘840, fig. 2A, cell layout 200A, contact pattern 208a-208n, 209, 242, par. [0083] [0084], fig. 8A-10, cells type 1B (second base layout cells), fig. 11, a first set of layout design of a first set of PUF cells 1102, fig. 2A, cells P2 and I2 are identical and are flipped/rotated from cells P1 and I1, respectively, also see fig. 2B-2L);
forming connections in the pattern of each of the first plurality of base layout cells (‘840, fig. 2A-2L, par. [0070] – [0072], [0077], [0083] – [0085]);
forming connections in the pattern of each of the second plurality of base layout cells (‘840, fig. 2A-2L, par. [0070] – [0072], [0077], [0083] – [0085]);
arranging the first and second pluralities of base layout cells in a sequence (‘840, fig. 8A-10, sequence such as column arranged “cell Typ1A- cellType1B- cell Typ1A- cellType1B” or row arranged 1st row: “cell Typ1B- cellType2B”and 2ndrow: cell Typ1A- cellType2A” and 3rd row and 4th row are repeated from 1st and 2nd row as same sequence to row 8);
defining first and second pluralities of circuits based on base marks of the first and second pluralities of base layout cells, respectively (‘840, fig. 2A, x-direction, line 290 and y-direction 204, see par. [0071] [0076] [0083]); and
connecting the first and the second pluralities of circuits (‘840, fig. 8A-10, ST1a, ST2, and St1B).
As per claim 17: Lee discloses the method of claim 16, wherein arranging the first and second pluralities of base layout cells comprises arranging the first and second pluralities of base layout cells in an alternative configuration (‘840, fig. 8A-9D, alternative arrangement such as column arranged “cell Typ1A- cellType1B- cell Typ1A- cellType1B” or row arranged 1st row: “cell Typ1B- cellType2B”and 2ndrow: cell Typ1A- cellType2A” and 3rd row and 4th row are repeated from 1st and 2nd row as same sequence to row 8).
As per claim 18: Lee discloses method of claim 16, wherein arranging the first and second pluralities of base layout cells comprises arranging the first and second pluralities of base layout cells in a random pattern (‘840, fig. 10, cells 1002 are random arrangement, par. [0376]).
As per claim 19: Lee discloses method of claim 16, wherein arranging the first and second pluralities of base layout cells comprises arranging positions of the first and second pluralities of base layout cells with an electronic design automation tool (‘840, fig. 13, and also see par. [0415], EDA tool).
As per claim 20: Lee discloses method of claim 16, wherein the first and the second pluralities of circuits comprise one or more of an inverter, an NAND gate, a NOR gate, and an AND-OR-INVERTER gate (‘840, fig. 1A).
As per claims 1-15: are also rejected as same breath as above because claims 1-15 are broader scopes of claims 16-20 as single cell layout. Hence, claims 1-15 are rejected by Lee’s fig. 1A-7).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10, 13-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Do et al., (U.S. Pub. 2022/0189944).
As per claim 1: Do discloses a method, comprising:
placing a base layout cell in a layout (standard cell) (‘944, fig. 1-15, CR1, par. [0035]), wherein the base layout cell comprises:
first and second active area layer patterns parallel to each other (‘944, fig. 1-15, first active area AR1 and second active region AR2, par. [0037]);
first contact layer patterns traversing over the first active area layer pattern (‘944, fig. 1-15, source/drain contact CA11-CA14 and gate contacts CB11-CB13 in first active region AR1);
second contact layer patterns traversing over the second active area layer pattern (‘944, fig. 1-15, source/drain contact CA15-CA17 in second active region AR2); and
conductive gate layer patterns traversing over the first and second active area layer patterns (‘944, fig. 1-15, conductive gate pattern G1-G3 traversing over the first and second active area layer patterns, par. [0037]);
connecting the first and second contact layer patterns to represent a circuit (‘944, first routing wiring IW11, IW12, CW11, CW12 and OW1, and a second routing wiring DW1, par. [0037], and also see fig. 3-11); and
defining the circuit based on a base mark of the base layout cell (‘944, fig. 1-15, cell region CR1, par. [0036]).
As per claim 2: Do discloses the method of claim 1, wherein the circuit comprises one or more of an inverter functional cell, an NAND functional cell, a NOR functional cell, and an AND-OR-INVERTER functional cell (‘944, fig. 1-15, par. [0011], and also see par. [0120], NAND cell).
As per claim 3: Do discloses the method of claim 1, wherein connecting the first and second contact layer patterns comprises placing a contact pattern on the base layout cell, wherein the contact pattern connect a plurality of contact layer patterns among the first and second contact layer patterns (‘994, fig. 1-15, par. [0043], CA11 to CA17 and connect contact by first routing wiring IW11, IW12, CW11, CW12 and OW1, and a second routing wiring DW1, see par. [0050] – [0054])).
As per claim 4: Do discloses the method of claim 1, wherein defining the circuit comprises defining a boundary of the base layout cell indicated by the base mark (‘944, par. [0008], par. [0059] –[0061], the boundary of the first cell region CR1).
As per claim 5: Do discloses the method of claim 1, wherein placing the base layout cell comprises selecting the base layout cell based on a layout cell pitch value (‘944, par. [0008], gate pitches, par. [0011] and DRC).
As per claim 6: Do discloses the method of claim 1, further comprising connecting a metal layer pattern of the base layout cell to a power supply, ground, or a combination thereof (‘944, fig. 1-15, VDD, VCC).
As per claim 7: Do discloses the method of claim 1, wherein each of the conductive gate layer patterns is adjacent to two of the first and second contact layer patterns (‘944, fig. 1-15, each of gate layer patterns G1-G3 is adjacent to first and second contact layer pattern CA11-CA17).
As per claim 8: Do discloses the method of claim 1, wherein the base layout cell further comprises a cut-metal layer pattern between the first and second active area layer patterns (‘944, fig. 1-15, cutting mask pattern routing level M1, par. [0176]) wherein a first distance between the cut-metal layer pattern and the first active area layer patterns is different from a second distance between the cut-metal layer pattern and the second active area layer patterns (‘944, fig. 1-15, CW12 vs. CW11 as well as IW12).
As per claim 9: Do discloses a method, comprising:
placing a first base layout cell in a layout (standard cell) (‘944, fig. 1-15, CR1, par. [0035]), wherein the first base layout cell comprises:
a first pattern representing active areas of a plurality of transistors (‘944, fig. 12-15, active region AR1 of a plurality of transistor CR1, CR2, and/or CR3);
a second pattern representing gate contacts of the plurality of transistors (’944, 12-15, gate contact CB11-CB13); and
a third pattern representing source/drain (S/D) contacts of the plurality of transistors (‘944, fig. 12-15, S/D contacts CA11-CA17);
placing a second base layout cell in the layout, wherein the first and second base layout cells are identical (‘944, fig. 13 and fig. 15, second base layout CR2 is identical to CR1, par. [0035] CR1 is a 2-input AND (AND2) cell and par. [0110] CR2 is a 2-input AND (AND2) cell);
forming connections in the third pattern of the first base layout cell to represent a first circuit (‘944, fig. 13 and fig. 15, CW11 and CW12 in CR1);
forming connections in the third pattern of the second base layout cell to represent a second circuit (‘944, fig. 13 and fig. 15, CW11 and CW12 in CR2);
defining the first and second circuits based on base marks of the first and second base layout cells (‘994, fig. 13, CR1 and CR2 and fig. 15, CR1 and CR3 and also see cell separation pattern I1a – I1d); and
connecting the first and the second circuits (‘944, fig. 13, CR1 and CR2 are connected and fig. 15, CR1 and CR3 are connected).
As per claim 10: Do discloses the method of claim 9, wherein placing the second base layout cell comprises arranging the second base layout cell adjacent to the first base layout cell (‘944, fig. 13 and fig. 13, CR1 adjacent to CR2 and/or CR3).
As per claim 13: Do discloses the method of claim 9, wherein the first and second circuits are different (‘994, fig. 15, CR1 is a AND2 cell, see par. [0035]; and CR3 is NAND2 cell, see par. [0120]).
As per claim 14: Do discloses the method of claim 9, wherein the first and second circuits comprise one or more of an inverter functional cell, an NAND functional cell, a NOR functional cell, and an AND-OR- INVERTER functional cell (‘944, par. [0035] CR1 is a 2-input AND (AND2) cell, see par. [0035]; and CR3 is NAND2 cell, see par. [0120]).
As per claim 15: Do discloses the method of claim 9, wherein the first base layout cell further comprises a cut-metal layer pattern separating the active areas into a p-type transistor area and an n-type transistor area (‘944, fig. 5, p-type 160 and n-type 260, par. [0079]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do et al., (U.S. Pub. 2022/0189944) in view of Lee et al., (U.S. Pub. 2020/0136840).
As per claim 11: Do does not teaches wherein placing the second base layout cell comprises flipping the second base layout cell with respect to the first base layout cell.
Lee teaches placing the second base layout cell comprises flipping the second base layout cell with respect to the first base layout cell (‘840, fig. 3A-3A, cell I2 is flipped/rotated from I1 and similar to P2 is flipped/rotated from P1 and also see fig. 5A-5E).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Lee and Do to change position of the corresponding set of conductive feature layout pattern by rotate/flip cell for occupy less area of circuit layout (‘840, par. [0415]).
As per claim 12: Do teaches layout design tool for placing the first and second base layout cells comprises arranging position of the first and second base layout cells (‘944, fig. 24, layout design tool 32 and placement and routing tool 34 that includes DRC, ERC, and LVS, see par. [0169])
Do does not implicitly teach in an electrotonic design automation (EDA)
Lee teaches the EDA is used to generate a layout design of an integrated circuit device.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to understand that Do’s layout design tool such as DRC, ERC, and LVS is/are Lee’s EDA being is well-known.
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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