DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 and 15-27 in the reply filed on 04/01/2026 is acknowledged.
Claims 8-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/01/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0061115 to Chen et al. (hereinafter Chen).
With respect to claim 1, Chen discloses a conductive via (e.g., interconnect structure 620 including a conductive via embedded in the molding compound, see the annotated Fig. 7 below) (Chen, Figs. 6-7, ¶0022-¶0027, ¶0037, ¶0056-¶0061) comprising:
a first end (6121a) (Chen, Fig. 7, ¶0058) and a second end (6131a);
a first portion (6121) (Chen, Fig. 7, ¶0058) adjacent to the first end (6121a);
a second portion (6131) (Chen, Fig. 7, ¶0058) adjacent to the second end (6131a); and
a middle portion (6132) (Chen, Fig. 7, ¶0058) located between the first portion (6121) and the second portion (6131),
wherein the conductive via is comprised of metal grains (e.g., with average grain size (a), (b), and (c)) (Chen, Fig. 7, ¶0059-¶0060),
wherein the metal grains in the first portion (6121) (Chen, Fig. 7, ¶0059) have a first grain size (a);
wherein the metal grains in the second portion (6131) (Chen, Fig. 7, ¶0059) have a second grain size (c);
wherein the metal grains in the middle portion (6132) (Chen, Fig. 7, ¶0059) have a third grain size (b);
wherein the first grain size (a) (Chen, Fig. 7, ¶0060) is greater than the third grain size (b); and
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wherein the second grain size (c) (Chen, Fig. 7, ¶0060) is greater than the third grain size (b).
Regarding claim 5, Chen discloses the conductive via of claim 1. Further, Chen discloses the conductive via, wherein the first grain size (a) is a maximum grain size, and wherein the maximum grain size (a) is (e.g., from 200 nm to 800 nm) (Chen, Figs. 6-7, ¶0047, ¶0072, ¶0079) (Note that a specific example in the prior art which is within a claimed range anticipates the range, M.P.E.P. §2131.03) from 200 to 1000 nanometers (nm).
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0008815 to Park et al. (hereinafter Park).
With respect to claim 15, Park discloses a semiconductor device (e.g., integrated circuit, see the annotated Fig. 2 below) (Park, Figs. 2-3, ¶0005-¶0018, ¶0041-¶0072) comprising:
a metal interconnection (e.g., through-electrode 20) (Park, Figs. 2-3, ¶0045-¶0048, ¶0066-¶0071) comprising:
a copper core (25) (Park, Figs. 2-3, ¶0047, ¶0070); and
a titanium-copper alloy (e.g., metal seed layer between the barrier layer 23 and the metal layer 25, and including an alloy layer of Ti/Cu) (Park, Figs. 2-3, ¶0046, ¶0070) surrounding the copper core (25).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0061115 to Chen in view of Fang et al. (US 2016/0307823, hereinafter Fang).
Regarding claims 2-3, Chen discloses the conductive via of claim 1. Further, Chen does not specifically disclose the conductive via, wherein the conductive via has a critical dimension of from 1 to 10 micrometers (mm) (as claimed in claim 2); wherein the conductive via has an aspect ratio of from 5 to 20 (as claimed in claim 3).
However, Fang teaches forming a conductive via (102) (Fang, Fig. 3A, ¶0060-¶0066) including portions of conductive material (e.g., copper) with different grain sizes, and having aspect ratio of width to height of the conductive via (102) that is greater than 1:3 or about 1:20, and with the width greater than 0.3 mm or greater than 0.5 mm, to provide interconnect structure including conductive vias with controlled interfaces to prevent break of subsequent material layers over the conductive vias to improve reliability of the semiconductor device (Fang, ¶0044-¶0045, ¶0060-¶0066).
The claimed ranges overlap the ranges of Fang. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Chen by forming high aspect ratio conductive vias including materials with different grain sizes as taught by Fang to have the conductive via, wherein the conductive via has a critical dimension of from 1 to 10 micrometers (mm) (as claimed in claim 2); wherein the conductive via has an aspect ratio of from 5 to 20 (as claimed in claim 3), in order to provide interconnect structure including conductive vias with controlled interfaces to prevent break of subsequent material layers over the conductive vias to improve reliability of the semiconductor device (Fang, ¶0044-¶0045, ¶0060-¶0066).
Claims 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0061115 to Chen.
Regarding claim 4, Chen discloses the conductive via of claim 1. Further, Chen does not specifically disclose the conductive via, wherein the first grain size is greater than the second grain size.
However, Chen teaches an embodiment, wherein the upper portion (8091/8092) (Chen, Fig. 8B, ¶0062-¶0064) has average grain sizes different from that of the lower portion (8071), specifically the average grain size of the lower portion (8071) is greater than that of the upper portion (8091/8092), to obtain interconnect structure including conductive vias with different grain sizes to provide high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, Fig. 7, ¶0022).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Chen by forming conductive vias including materials with different grain sizes as taught by Chen to have the conductive via, wherein the first grain size is greater than the second grain size, in order to obtain interconnect structure including conductive vias with different grain sizes to provide high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, ¶0022, ¶0059, ¶0064).
Regarding claims 6-7, Chen discloses the conductive via of claim 5. Further, Chen discloses the conductive via, wherein: the first end (6121a) (Chen, Fig. 7, ¶0061) is distanced from the second end (6131a) by a height; the first portion (6121), the second portion (6131), and the middle portion (6132) each have a subheight, but does not specifically disclose that a subheight equal to 1/3 of the height; the first portion has an average grain size of greater than 0.5 of the maximum grain size; the second portion has an average grain size of greater than 0.5 of the maximum grain size; and the middle portion has an average grain size of less than 0.5 of the maximum grain size (as claimed in claim 6); wherein: the first portion has an average grain size of greater than 0.6 of the maximum grain size; the second portion has an average grain size of less than 0.6 of the maximum grain size; and the middle portion has an average grain size of less than 0.4 of the maximum grain size (as claimed in claim 7).
However, Chen teaches that heights (H1/H2) (Chen, Fig. 3, ¶0046-¶0049) of conductive layers (302/301) having different grain sizes can be different or the same (e.g., H1=H2, of about 5 mm); the average size (b) of the conductive layer (302) is below 200 nm, and the average grain size (a) of the conductive layer (301) is between 200 nm and 800 nm. The average size (a) is about 1.5 greater than the average size (b) (Chen, Fig. 3, ¶0044). Further, Chen teaches that controlled interface between the coarse average grain size and fine average grain size within the interconnect structure impacts the properties of electrical connections and electromigration resistance of the copper interconnect (Chen, ¶0022-¶0027).
Thus, Chen recognizes that the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion impact the properties of the copper interconnect. Thus, the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion as Chen has identified the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion, such that a subheight equal to 1/3 of the height; the first portion has an average grain size of greater than 0.5 of the maximum grain size; the second portion has an average grain size of greater than 0.5 of the maximum grain size; and the middle portion has an average grain size of less than 0.5 of the maximum grain size (as claimed in claim 6); wherein: the first portion has an average grain size of greater than 0.6 of the maximum grain size; the second portion has an average grain size of less than 0.6 of the maximum grain size; and the middle portion has an average grain size of less than 0.4 of the maximum grain size (as claimed in claim 7), in order to improve properties of electrical connections and electromigration resistance of the copper interconnect as taught by Chen (¶0022-¶0027) (¶0016-¶0017) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Chen by optimizing the average grain sizes and heights of the coarse average grain size portion and fine average grain size portion as taught by Chen to have the conductive via, wherein: a subheight equal to 1/3 of the height; the first portion has an average grain size of greater than 0.5 of the maximum grain size; the second portion has an average grain size of greater than 0.5 of the maximum grain size; and the middle portion has an average grain size of less than 0.5 of the maximum grain size (as claimed in claim 6); wherein: the first portion has an average grain size of greater than 0.6 of the maximum grain size; the second portion has an average grain size of less than 0.6 of the maximum grain size; and the middle portion has an average grain size of less than 0.4 of the maximum grain size (as claimed in claim 7), in order to improve properties of electrical connections and electromigration resistance of the copper interconnect (Chen, ¶0022-¶0027).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0181179 to Lin et al. (hereinafter Lin) in view of Park (US 2014/0008815).
With respect to claim 15, Lin discloses a semiconductor device (e.g., integrated circuit device, see the annotated Fig. 9 below) (Lin, Figs. 9-10, ¶0015-¶0026) comprising:
a metal interconnection (e.g., through-silicon via TSV 60 and deep vias 62) (Lin, Figs. 9-10, ¶0019-¶0023) comprising:
a copper core (e.g., copper filling material) (Lin, Figs. 9-10, ¶0023); and
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a copper alloy (e.g., metal seed layer between the barrier layer 54 and the metal layer 60/62) (Park, Figs. 2-3, ¶0021) surrounding the copper core (60/62).
Further, Lin does not specifically disclose a titanium-copper alloy.
However, Park teaches forming through-electrode 20) (Park, Figs. 2-3, ¶0045-¶0048, ¶0066-¶0071) comprising a copper core (25) (Park, Figs. 2-3, ¶0047, ¶0070), and a seed layer between the barrier layer (23) and the metal layer (25), and including an alloy layer of Ti/Cu (Park, Figs. 2-3, ¶0046, ¶0070) surrounding the copper core (25).
It would have been obvious to one having ordinary skill before the effective filing date of the invention to have substituted the material of the seed layer of Lin with the material of the seed layer as taught by Park to have a titanium-copper alloy. All the claimed elements were known in the prior art and one skilled in the art could have substituted the elements as claimed by known methods with no change in their respective functions, and the substitution would have yielded predictable results to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lin by forming a seed layer including an alloy layer of Ti/Cu as taught by Park to have a titanium-copper alloy, in order to improve adhesion of the metal layer formed by the plating method to provide a semiconductor device with improved reliability (Park, ¶0005, ¶0070).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0181179 to Lin in view of Park (US 2014/0008815) as applied to claim 15, and further in view of Chen (2015/0061115).
Regarding claim 16, Lin in view of Park discloses the semiconductor device of claim 15. Further, Lin does not specifically disclose that the copper core is comprised of copper grains; the copper core includes a top portion, a bottom portion, and middle portion between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size; the copper grains in the bottom portion have a second average grain size; the copper grains in the middle portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size.
However, Chen teaches forming a conductive via (e.g., interconnect structure 620 including a conductive via embedded in the molding compound) (Chen, Figs. 6-7, ¶0022-¶0027, ¶0037, ¶0047, ¶0056-¶0061), wherein the copper core is comprised of copper grains (e.g., with average grain size (a), (b), and (c)) (Chen, Fig. 7, ¶0059-¶0060); the copper core includes a top portion (6131) (Chen, Fig. 7, ¶0058), a bottom portion (6121), and middle portion (6132) between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size (c) (Chen, Fig. 7, ¶0060); the copper grains in the bottom portion have a second average grain size (a); the copper grains in the middle portion have a third average grain size (b); the first average grain size (c) is greater than the third average grain size (b); and the second average grain size (a) is greater than the third average grain size (b). In Chen, the interconnect structures comprising copper layers with different grain sizes provide high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, ¶0022).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lin/Park by forming a conductive interconnect structure as taught by Chen to have the semiconductor device, wherein the copper core is comprised of copper grains; the copper core includes a top portion, a bottom portion, and middle portion between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size; the copper grains in the bottom portion have a second average grain size; the copper grains in the middle portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size, in order to provide improved interconnect structures having high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, ¶0022, ¶0058-¶0060).
Regarding claim 17, Lin in view of Park and Chen discloses the semiconductor device of claim 16. Further, Lin discloses the semiconductor device, wherein the metal interconnection (e.g., through-silicon via TSV 60 and deep vias 62) (Lin, Figs. 9-10, ¶0019-¶0023) further comprises a titanium layer (e.g., barrier layer 54 including titanium) surrounding the titanium-copper alloy (e.g., the seed layer including Ti/Cu alloy in view of Park) at the top portion of the copper core.
Regarding claims 18-20, Lin in view of Park and Chen discloses the semiconductor device of claim 17. Further, Lin does not specifically disclose the semiconductor device, wherein the metal interconnection further comprises a titanium nitride layer surrounding the titanium-copper alloy below the top portion of the copper core and surrounding the titanium layer at the top portion of the copper core (as claimed in claim 18); wherein the metal interconnection further comprises a titanium nitride layer surrounding the titanium-copper alloy (as claimed in claim 19); wherein the metal interconnection further comprises an outer titanium layer surrounding the titanium nitride layer (as claimed in claim 20).
However, Park teaches forming barrier layer (23) (Park, Figs. 2-3, ¶0047, ¶0069-¶0070) including titanium, titanium nitride, titanium/titanium nitride, or combination thereof to prevent diffusion of the metal in the metal layer (25) into the semiconductor substrate (10), and the seed layer of Ti/Cu alloy between the barrier layer (23) and the metal layer (25).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lin/Park/Chen by forming a barrier layer including combination of titanium/titanium nitride and titanium layer surrounding the seed layer of Ti/Cu alloy and the copper interconnect having the top portion and the bottom portion as taught by Park to have the semiconductor device, wherein the metal interconnection further comprises a titanium nitride layer surrounding the titanium-copper alloy below the top portion of the copper core and surrounding the titanium layer at the top portion of the copper core (as claimed in claim 18); wherein the metal interconnection further comprises a titanium nitride layer surrounding the titanium-copper alloy (as claimed in claim 19); wherein the metal interconnection further comprises an outer titanium layer surrounding the titanium nitride layer (as claimed in claim 20), in order to prevent diffusion of the metal into the semiconductor substrate, and to improve adhesion of the metal layer, and thus to provide a semiconductor device with improved reliability (Park, ¶0005, ¶0047, ¶0069-¶0070).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0227479 to Feng et al. (hereinafter Feng).
With respect to claim 21, Feng discloses a conductive via (e.g., metal interconnect including a via, see the annotated Fig. 6 and Fig. 2) (Feng, Figs. 6, 7b, ¶0015-¶0020, ¶0034-¶0056, ¶0067) comprising:
a first end (e.g., bottom/top end of the metal layer 18/19) (Feng, Figs. 6, 7b, ¶0052) and a second end (e.g., top/bottom end of the metal layer 18/19);
a first portion (e.g., bottom/top portion of the metal layer 18/19) (Feng, Figs. 6, 7b, ¶0052) adjacent to the first end;
a second portion (e.g., top/bottom portion of the metal layer 18/19) adjacent to the second end; and
a middle portion (e.g., at the junction between the metal layers 18 and 19) (Feng, Figs. 6, 7b, ¶0052) located between the first portion and the second portion.
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Further, Feng does not specifically disclose that voids within the conductive via are concentrated in the middle portion, and wherein the first portion and the second portion are each substantially free of voids.
However, Feng teaches that conventionally voids are located at the grain boundary (8a) (Feng, Figs. 1-2, ¶0007). Additionally, voids defects are attributed to carbon impurity content (Feng, Figs. 6, 7b, ¶0056), and carbon impurity content is concentrated (e.g., as sown in Fig. 7b, the carbon impurities are greatest in the middle portion at the interface between the metal layers 18/19) (Feng, Figs. 6, 7b, ¶0042-¶0052) at the interface between the first metal layer (18) (Feng, Figs. 6, 7b, ¶0050) having specific grain sizes after first anneal process and the second metal layer (19) having specific grain sizes after second anneal process, to provide metal interconnect having higher device performance and reliability (Feng, ¶0015, ¶0056, ¶0067).
Thus, Feng recognizes that carbon impurity content impacts the presence of voids and device performance and reliability. Thus, carbon impurity content is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, carbon impurity content within first/second and middle portions of the interconnect as Feng has identified carbon impurity content as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific carbon impurity content within first/second and middle portions, such that voids within the conductive via are concentrated in the middle portion, and wherein the first portion and the second portion are each substantially free of voids, in order to provide metal interconnect having higher device performance and reliability as taught by Feng (¶0015, ¶0056, ¶0067) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng by optimizing deposition of the first and second metal layers and anneal processes controlling carbon impurity content in the conductive vias as taught by Feng to have the conductive via, wherein voids within the conductive via are concentrated in the middle portion, and wherein the first portion and the second portion are each substantially free of voids, in order to provide metal interconnect having higher device performance and reliability (Feng, ¶0015, ¶0056, ¶0067).
Claims 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0227479 to Feng in view of Park (US 2014/0008815) and Yu et al. (US 2012/0070982, hereinafter Yu).
Regarding claim 22, Feng discloses the conductive via of claim 21. Further, Feng discloses the conductive via, further comprising: a copper core (18/19, copper) (Feng, Fig. 6, ¶0052); and a copper seed layer (17) (Feng, Fig. 6, ¶0039-¶0040) surrounding the copper core (18/19), but does not specifically disclose (1) a titanium-copper alloy layer, (2) wherein the titanium-copper alloy layer has a greater lateral thickness in the middle portion than in the second portion.
Regarding (1), Park teaches forming through-electrode 20) (Park, Figs. 2-3, ¶0045-¶0048, ¶0066-¶0071) comprising a copper core (25) (Park, Figs. 2-3, ¶0047, ¶0070), and a seed layer between the barrier layer (23) and the metal layer (25), and including an alloy layer of Ti/Cu (Park, Figs. 2-3, ¶0046, ¶0070) surrounding the copper core (25), to improve adhesion of the metal layer formed by the plating method to provide a semiconductor device with improved reliability (Park, ¶0005, ¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng by forming a seed layer including an alloy layer of Ti/Cu as taught by Park to have a titanium-copper alloy, in order to improve adhesion of the metal layer formed by the plating method to provide a semiconductor device with improved reliability (Park, ¶0005, ¶0070).
Regarding (2), Yu teaches forming copper interconnect (Yu, Fig. 2E-2F, ¶0017-¶0034) comprising a seed layer (210) (Yu, Fig. 2E-2F, ¶0026) including copper alloy, wherein a thickness of the seed layer (210) (Yu, Fig. 2E-2F, ¶0031) is controlled at desired locations along the sidewalls (214) to provide inwardly sloped seed layer profile having a thickness at the lower portion of the sidewall more than twice the seed layer thickness at the upper portion of the sidewall, to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, Fig. 2E-2F, ¶0014, ¶0038, ¶0055).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng/Park by forming a seed layer having specific seed layer profile as taught by Yu, wherein the seed layer includes an alloy layer of Ti/Cu as taught by Park to have the conductive via, wherein the titanium-copper alloy layer has a greater lateral thickness in the middle portion than in the second portion, in order to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, ¶0014, ¶0038, ¶0055).
Regarding claim 23, Feng in view of Park and Yu discloses the conductive via of claim 22. Further, Feng discloses the conductive via, wherein the copper seed layer (17) (Feng, Fig. 6, ¶0039-¶0040) has a thickness between 100 and 200 nm, but does not specifically disclose that the titanium-copper alloy layer has a lateral thickness of from 40 nanometers to 80 nanometers in the middle portion and a lateral thickness of from 1 nanometer to 30 nanometers in the second portion.
However, Yu teaches that a thickness of the seed layer (210) (Yu, Fig. 2E-2F, ¶0031) is controlled at desired locations along the sidewalls (214) to provide inwardly sloped seed layer profile having a thickness at the lower portion of the sidewall more than twice the seed layer thickness at the upper portion of the sidewall, to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, Fig. 2E-2F, ¶0014, ¶0038, ¶0055). The thickness of the seed layer at the bottom portion is between 2 and 10 nm, and the thickness of the seed layer at the upper portion is between 1 and 5 nm, and the thickness of the seed layer depends on feature size (Yu, Fig. 2E-2F, ¶0031).
Thus, Yu recognizes that the seed layer profile and specific thickness of the seed layer impacts the reliability of the conductive feature. Thus, the seed layer profile and specific thickness of the seed layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the seed layer profile and specific thickness of the seed layer as Yu has identified the seed layer profile and specific thickness of the seed layer result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific the seed layer profile and specific thickness of the seed layer, such that the sed layer has a lateral thickness of from 40 nanometers to 80 nanometers in the middle portion and a lateral thickness of from 1 nanometer to 30 nanometers in the second portion, in order to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature as taught by Yu (¶0014, ¶0038, ¶0055) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng/Park/Yu by optimizing the seed layer profile and specific thickness of the seed layer for the via having specific feature size as taught by Yu, wherein the seed layer includes an alloy layer of Ti/Cu as taught by Park to have the conductive via, wherein the titanium-copper alloy layer has a lateral thickness of from 40 nanometers to 80 nanometers in the middle portion and a lateral thickness of from 1 nanometer to 30 nanometers in the second portion, in order to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, ¶0014, ¶0038, ¶0055).
Regarding claim 24, Feng in view of Park and Yu discloses the conductive via of claim 22. Further, Feng discloses the conductive via, further comprising a barrier layer (16) (Feng, Fig. 6, ¶0038) surrounding the seed layer (17), but does not specifically disclose the titanium-copper alloy layer, wherein the barrier layer is in direct contact with the copper core at the second end.
However, Yu taches the seed layer having the seed layer profile and specific thickness of the seed layer (210) decreased at the upper portion of the feature, to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, ¶0014, ¶0038, ¶0055).
Thus, Yu recognizes that the seed layer profile and specific thickness of the seed layer at the upper portion of the feature impacts the reliability of the conductive feature. Thus, the seed layer profile and specific thickness of the seed layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the seed layer profile and specific thickness of the seed layer at the upper portion of the feature as Yu has identified the seed layer profile and specific thickness of the seed layer at the upper portion of the feature result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific the seed layer profile and specific thickness of the seed layer at the upper portion of the feature, such that the barrier layer is in direct contact with the copper core at the second end, in order to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature as taught by Yu (¶0014, ¶0038, ¶0055) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng/Park/Yu by optimizing the seed layer profile and specific thickness of the seed layer at the upper portion of the feature as taught by Yu, wherein the seed layer includes an alloy layer of Ti/Cu as taught by Park to have the conductive via, wherein the titanium-copper alloy layer, wherein the barrier layer is in direct contact with the copper core at the second end, in order to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, ¶0014, ¶0038, ¶0055).
Regarding claim 25, Feng in view of Park and Yu discloses the conductive via of claim 24. Further, Feng does not specifically disclose the conductive via, further comprising a titanium layer between the barrier layer and the titanium-copper alloy layer in the first portion, wherein the titanium layer is absent between the barrier layer and the copper core in the middle portion and in the second portion.
However, Park teaches forming a seed layer comprised of combination of Ti/Cu alloy, Ti/Pd, and Ti/Ni (Park, Figs. 2-3, ¶0046, ¶0070).
Further, Yu taches the seed layer having the seed layer profile and specific thickness of the seed layer (210) decreased at the upper portion of the feature, to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Yu, ¶0014, ¶0038, ¶0055).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng/Park/Yu by forming the seed layer comprised of combination of Ti/Cu alloy, Ti/Pd, and Ti/Ni as taught by Park, wherein the seed layer profile and specific thickness of the seed layer at the upper portion of the feature are optimized as taught by Yu to have the conductive via, further comprising a titanium layer between the barrier layer and the titanium-copper alloy layer in the first portion, wherein the titanium layer is absent between the barrier layer and the copper core in the middle portion and in the second portion, in order to improve adhesion of the metal layer formed by the plating method to provide a semiconductor device with improved reliability; to improve filling the feature with conductive materials from the bottom to the top by reducing buildup of conductive materials on the upper corners of the feature (Park, ¶0005, ¶0070; Yu, ¶0014, ¶0038, ¶0055).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0227479 to Feng in view of Lin (US 2016/0181179).
Regarding claim 26, Feng discloses the conductive via of claim 21. Further, Feng does not specifically disclose that the conductive via is a through-substrate via, and wherein the conductive via further comprises: a substrate through which the through-substrate via extends; deep conductive vias extending into an interconnect structure disposed on the substrate; and a redistribution line electrically connecting the through-substrate via to the deep conductive vias.
However, Lin teaches forming a semiconductor device (e.g., integrated circuit device) (Lin, Figs. 9-10, ¶0015-¶0026) comprising a metal interconnection (e.g., through-silicon via TSV 60 and deep vias 62) (Lin, Figs. 9-10, ¶0019-¶0023), the conductive via is a through-substrate via (60), and wherein the conductive via (60/62) further comprises: a substrate (22) through which the through-substrate via (60) extends; deep conductive vias (62) extending into an interconnect structure disposed on the substrate (22); and a redistribution line (66) electrically connecting the through-substrate via (60) to the deep conductive vias (62), to provide interconnect structure with reduced paths to the metal features on different metallization layers to improve power connection efficiency (Lin, ¶0028).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng by forming a semiconductor device comprising through-silicon via TSV and deep vias as taught by Lin to have the conductive via, wherein the conductive via is a through-substrate via, and wherein the conductive via further comprises: a substrate through which the through-substrate via extends; deep conductive vias extending into an interconnect structure disposed on the substrate; and a redistribution line electrically connecting the through-substrate via to the deep conductive vias, in order to provide through-substrate vias with improved electrical connections and to provide interconnect structure with reduced paths to the metal features on different metallization layers to improve power connection efficiency (Lin, ¶0002, ¶0006, ¶0019, ¶0028, ¶0031).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0227479 to Feng in view of Chen (2015/0061115).
Regarding claim 27, Feng discloses the conductive via of claim 21. Further, Feng discloses that metal grains in the first portion (18) (Feng, Fig. 6, ¶0046) have a first average grain size; the metal grains in the second portion (19) (Feng, Fig. 6, ¶0049) have a second average grain size, but does not specifically disclose that the metal grains in the middle portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size.
However, Chen teaches forming a conductive via (e.g., interconnect structure 620 including a conductive via embedded in the molding compound) (Chen, Figs. 6-7, ¶0022-¶0027, ¶0037, ¶0047, ¶0056-¶0061), wherein the copper core is comprised of copper grains (e.g., with average grain size (a), (b), and (c)) (Chen, Fig. 7, ¶0059-¶0060); the copper core includes a top portion (6131) (Chen, Fig. 7, ¶0058), a bottom portion (6121), and middle portion (6132) between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size (c) (Chen, Fig. 7, ¶0060); the copper grains in the bottom portion have a second average grain size (a); the copper grains in the middle portion have a third average grain size (b); the first average grain size (c) is greater than the third average grain size (b); and the second average grain size (a) is greater than the third average grain size (b). In Chen, the interconnect structures comprising copper layers with different grain sizes provide high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, ¶0022).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the conductive via of Feng by forming a conductive interconnect structure as taught by Chen to have the conductive via, wherein: metal grains in the first portion have a first average grain size; the metal grains in the second portion have a second average grain size; the metal grains in the middle portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size, in order to provide improved interconnect structures having high electrical conductivity connections, excellent electromigration resistance, and increased mechanical strength for high aspect ratio structures (Chen, ¶0022, ¶0058-¶0060).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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