DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II, corresponding to claims 1-8, 10-17 and 19-20 in the reply filed on June 02, 2026 is acknowledged. Claims 9 and 18 directed to the non-elected species are thereby withdrawn. As a result, claims 1-20 are currently pending.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/21/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-8, 12, 15, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SON, Kyoung Seok (US 20200127077 A1) “SON et al.”.
Regarding Independent Claim 1, SON et al. Figs. 2-3 discloses a semiconductor structure, comprising:
a first electrode (“electrode E2 of the storage capacitor SC” ¶ [0067]), disposed on a substrate (“a substrate 110” ¶ [0071]);
a second electrode (“gate electrode G1 may also be (and/or function as) the first electrode E1 of the storage capacitor SC” ¶ [0079]), disposed on the first electrode;
an insulating layer (“insulating layer 141” ¶ [0078]), disposed between the first electrode and the second electrode (Fig. 3 shows 141 is between E2 and E1/G1);
a channel layer (“the channel C1” ¶ [0081]), disposed on the second electrode;
a gate dielectric layer (“insulating layer 160” ¶ [0080]), disposed between the channel layer and the second electrode (Fig. 3 shows 160 is between E1/G1 and A1/C1);
a source electrode (“source electrode S1 and the drain electrode D1” ¶ [0081]), electrically connected to the first electrode (Fig. 2 shows E2 is electrically connected to the transistor D1. Source/drain can be used interchangeably depending on the circuit biases) and the channel layer (“source electrode S1 and the drain electrode D1 may form the channel C1 of the first transistor T1” ¶ [0081]); and
a drain electrode (“source electrode S1 and the drain electrode D1” ¶ [0081]), electrically connected to the channel layer (“source electrode S1 and the drain electrode D1 may form the channel C1 of the first transistor T1” ¶ [0081]).
Regarding Claim 4, SON et al. discloses the limitations of claim 1. SON et al. further discloses, further comprising a cap layer (“insulating layer 161” ¶ [0085]) covering the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer (Fig. 3 shows 161 covering first electrode E2, the insulating layer 141, the second electrode E1/G1, the gate dielectric layer 160 and the channel layer A1/C1).
Regarding Claim 5, SON et al. discloses the limitations of claim 4. SON et al. further discloses, wherein a material of the cap layer 161 comprises silicon nitride (SiN) (“insulating layer 161 may include an inorganic insulating material such as …. a silicon nitride” ¶ [0085]), silicon carbonitride (SiCN) or silicon oxynitride (SiON).
Regarding Claim 6, SON et al. discloses the limitations of claim 1. SON et al. further discloses, wherein the second electrode G1/E1 is electrically connected to a transistor disposed at the substrate (Fig. 2 shows G1/E1 is connected to T2).
Regarding Claim 7, SON et al. discloses the limitations of claim 1. SON et al. further discloses, further comprising a buffer layer (“A buffer layer 120” ¶ [0074]) disposed between the substrate and the first electrode (Fig. 3 shows 120 is between 110 and E2).
Regarding Claim 8, SON et al. discloses the limitations of claim 7. SON et al. further discloses, wherein a material of the buffer layer comprises SiN, SiCN or SiON (“The buffer layer 120 may include an inorganic insulating material such as a silicon oxide and/or a silicon nitride.” ¶ [0074]).
Regarding Independent Claim 12, SON et al. Figs. 4-14 manufacturing method of a semiconductor structure, comprising:
forming a first electrode (“to form a conductive layer, and the conductive layer is patterned by a photolithography process using a second mask to form …. a second electrode E2 of a storage capacitor SC” ¶ [0098]) on a substrate (“on a substrate 110” ¶ [0097]);
forming an insulating layer on the first electrode (“Referring to FIG. 6, a second insulating layer 141 is formed by depositing an inorganic insulating material.” ¶ [0099]);
forming a second electrode on the insulating layer (“The conductive layer is formed on the second insulating layer 141 by a conductive material, and the conductive layer is patterned by a photolithography process using a third mask to form a gate electrode G1 of the first transistor T1. The gate electrode G1 may also be the first electrode E1 of the storage capacitor SC.” ¶ [0099]);
forming a gate dielectric layer on the second electrode (“Referring to FIG. 7, the third insulating layer 160 is formed by depositing an inorganic insulating material.” ¶ [0100]);
forming a channel layer on the gate dielectric layer (“the oxide semiconductor layer is patterned by a photolithography process using a fourth mask to form a semiconductor member A1 and a semiconductor member A2.” ¶ [0100]); and
forming a source electrode and a drain electrode (“portions of the semiconductor member A2 that are exposed without being covered by the insulator 142 may be processed to form the source electrode S2 and the drain electrode D2.” ¶ [0102]), wherein the source electrode is electrically connected to the first electrode (Fig. 2 shows E2 is electrically connected to the transistor D1. Source/drain can be used interchangeably depending on the circuit biases) and the channel layer (“source electrode S1 and the drain electrode D1 may form the channel C1 of the first transistor T1” ¶ [0081]), and the drain electrode is electrically connected to the channel layer (“source electrode S1 and the drain electrode D1 may form the channel C1 of the first transistor T1” ¶ [0081]).
Regarding Claim 15, SON et al. discloses the limitations of claim 12. SON et al. further discloses, wherein a forming method of the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer comprises:
forming a first electrode material layer (“a conductive material such as a metal is deposited on the first insulating layer 140 by a sputtering method to form a conductive layer” ¶ [0098]), an insulating material layer (“a second insulating layer 141 is formed by depositing an inorganic insulating material.” ¶ [0099]), a second electrode material layer (“form a gate electrode G1” ¶ [0099]), a gate dielectric material layer (“third insulating layer 160 is formed by depositing an inorganic insulating material” ¶ [0100]) and a channel material layer (“form an oxide semiconductor layer” ¶ [0100]) in sequence on the substrate (“on a substrate 110” ¶ [0097]);
performing a first patterning process (“conductive layer is patterned by a photolithography process” ¶ [0098], ¶ [0099]) on the first electrode material layer E2, the insulating material layer 141, the second electrode material layer G1/E1, the gate dielectric material layer 160 and the channel material layer A1/C1;
performing a second patterning process (“oxide semiconductor layer is patterned by a photolithography process” ¶ [0100]) on the channel material layer A1/C1, the gate dielectric material layer 160, the second electrode material layer G1/E1 and the insulating material layer 141; and
performing a third patterning process (“patterned by a photolithography process using a sixth mask to form the source electrode 51 of the first transistor T1,” ¶ [0102]) on the channel material layer A1/C1 and the gate dielectric material layer 160.
Regarding Claim 17, SON et al. discloses the limitations of claim 12. SON et al. further discloses, further comprising forming a buffer layer (“a buffer layer 120” ¶ [0097]) on the substrate 110 before forming the first electrode E2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200127077 A1) “SON et al.” in view of (US 20210020667 A1) “Yamazaki et al.”.
Regarding Claim 2, SON et al. discloses the limitations of claim 1, However, SON et al. does not disclose, wherein the second electrode and the insulating layer expose a portion of the first electrode.
In the similar field of endeavor of TFT transistors, Yamazaki et al. Figs. 13-14 discloses wherein the second electrode 205 and the insulating layer 214 and 150 expose (Figs. 13 and 14 shows the second electrode 205 expose a portion of 120 and 214 and 150 expose a portion of 120 through the openings) a portion of the first electrode 120.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the electrodes of SON et al. with the electrodes of Yamazaki et al. in order to provide a semiconductor device having stable electrical characteristics (Yamazaki, ¶ [304]).
Regarding Claim 13, SON et al. discloses the limitations of claim 12, However, SON et al. does not disclose, wherein the second electrode and the insulating layer expose a portion of the first electrode.
In the similar field of endeavor of TFT transistors, Yamazaki et al. Figs. 13-14 discloses wherein the second electrode 205 and the insulating layer 214 and 150 expose (Figs. 13 and 14 shows the second electrode 205 expose a portion of 120 and 214 and 150 expose a portion of 120 through the openings) a portion of the first electrode 120.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the electrodes of SON et al. with the electrodes of Yamazaki et al. in order to provide a semiconductor device having stable electrical characteristics (Yamazaki, ¶ [304]).
Claims 3, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200127077 A1) “SON et al.” in view of (US 20150055047 A1) “Chang et al.”.
Regarding Claim 3, SON et al. discloses the limitations of claim 1. SON et al. does not disclose, wherein the channel layer exposes a portion of the second electrode (Fig. 3 shows channel layer A1/C1 exposes a portion of G1/E1).
However, SON et al. does not disclose, the gate dielectric layer exposes a portion of the second electrode.
In the similar field of endeavor of TFT transistors, Chang et al. Fig. 3 discloses, the gate dielectric layer (“The "gate insulator" of the oxide transistor may be formed from the layer of interlayer dielectric (i.e., layers 68 and 70)” ¶ [0036]) exposes a portion (Fig. 3 shows exposed portion of 66’ where the contact is connected) of the second electrode (“The capacitor may have a second terminal formed from metal layer 66'” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the electrodes of SON et al. with the exposed second electrodes of Chang et al. in order to provide optimum performance (Chang et al., ¶ [0031]).
Regarding Claim 14, SON et al. discloses the limitations of claim 12. SON et al. does not disclose, wherein the channel layer exposes a portion of the second electrode (Fig. 3 shows channel layer A1/C1 exposes a portion of G1/E1).
However, SON et al. does not disclose, the gate dielectric layer exposes a portion of the second electrode.
In the similar field of endeavor of TFT transistors, Chang et al. Fig. 3 discloses, the gate dielectric layer (“The "gate insulator" of the oxide transistor may be formed from the layer of interlayer dielectric (i.e., layers 68 and 70)” ¶ [0036]) exposes a portion (Fig. 3 shows exposed portion of 66’ where the contact is connected) of the second electrode (“The capacitor may have a second terminal formed from metal layer 66'” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the electrodes of SON et al. with the exposed second electrodes of Chang et al. in order to provide optimum performance (Chang et al., ¶ [0031]).
Claims 10, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over SON, Kyoung Seok (US 20200127077 A1) “SON et al.” in view of (US 20080038884 A1) “Hwang et al.”.
Regarding Claim 10, SON et al. discloses the limitations of claim 1. However, SON et al. does not disclose, wherein the source electrode and the drain electrode comprise doping regions disposed in the channel layer.
In the similar field of endeavor of TFT transistors, Hwang et al. Figs. 3F-3G and 5C-5D discloses, wherein the source electrode and the drain electrode comprise doping regions disposed in the channel layer (“the N- ions are injected into the source and drain regions 124a and 124c of the NMOS TFT as well as the exposed source and drain regions 114a and 114c of the PMOS TFT at a lower dose than the P+ ions injected into the source and drain regions 114a and 114c of the PMOS TFT and the N+ ions injected into the source and drain regions 124a and 124c of the NMOS TFT. Therefore, the N- ions injected into the exposed source and drain regions 114a and 114c of the PMOS TFT and the source and drain regions 124a and 124c of the NMOS TFT do not affect the source and drain regions 114a and 114c of the PMOS TFT nor the source and drain regions 124a and 124c of the NMOS TFT.” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify source drain region of SON et al. with source drain region comprising doping regions disposed in the channel layer of Hwang et al. in order to reduce production cost by simplifying the process (Hwang et al., ¶ [0045]).
Regarding Claim 16, SON et al. discloses the limitations of claim 12. SON et al. further discloses, further comprising forming a cap layer (“Referring to FIG. 10, an inorganic insulating material is deposited to form a fourth insulating layer 161” ¶ [0103]) to cover the first electrode E2, the insulating layer 141, the second electrode G1/E1, the gate dielectric layer 160 and the channel layer A1/C1 (Fig. 10 shows 161 covers the first electrode E2, the insulating layer 141, the second electrode G1/E1, the gate dielectric layer 160 and the channel layer A1/C1) after forming the channel layer A1/C1.
However, SON et al. does not disclose forming cap layer before forming the source electrode and the drain electrode.
In the similar field of endeavor of TFT transistors, Hwang et al. Figs. 3F-3G and 5C-5D discloses, forming cap layer before forming the source electrode and the drain electrode (“after an interlayer insulating layer 132 is formed on the entire surface of the substrate 101 on which the channel, the source region, and the drain region 114e, 114a, and 114c are formed, a source contact hole 136 and a drain contact hole 138 are formed by a third mask process to penetrate the gate insulating layer 112 and the interlayer insulating layer 132 and expose the source and drain regions 114a and 114c of the PMOS TFT. Subsequently, as illustrated in FIG. 5D, source and drain electrodes 115 and 116 of the PMOS TFT are formed by a fourth mask process to be connected with the source and drain regions 114a and 114c of the PMOS TFT through the source contact hole 136 and the drain contact hole 138.” ¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify forming cap layer of SON et al. with the method of forming cap layer of electrodes of Hwang et al. in order to reduce production cost by simplifying the process (Hwang et al., ¶ [0045]).
Regarding Claim 19, SON et al. discloses the limitations of claim 12. However, SON et al. does not disclose, wherein the source electrode and the drain electrode comprise doping regions disposed in the channel layer.
In the similar field of endeavor of TFT transistors, Hwang et al. Figs. 3F-3G and 5C-5D discloses, wherein the source electrode and the drain electrode comprise doping regions disposed in the channel layer (“the N- ions are injected into the source and drain regions 124a and 124c of the NMOS TFT as well as the exposed source and drain regions 114a and 114c of the PMOS TFT at a lower dose than the P+ ions injected into the source and drain regions 114a and 114c of the PMOS TFT and the N+ ions injected into the source and drain regions 124a and 124c of the NMOS TFT. Therefore, the N- ions injected into the exposed source and drain regions 114a and 114c of the PMOS TFT and the source and drain regions 124a and 124c of the NMOS TFT do not affect the source and drain regions 114a and 114c of the PMOS TFT nor the source and drain regions 124a and 124c of the NMOS TFT.” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify source drain region of SON et al. with source drain region comprising doping regions disposed in the channel layer of Hwang et al. in order to reduce production cost by simplifying the process (Hwang et al., ¶ [0045]).
Claims 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200127077 A1) “SON et al.” in view of (US 20230389358 A1) “CHO et al.”.
Regarding Claim 11, SON et al. discloses the limitations of claim 1. SON et al. further discloses, wherein the source electrode comprises a first conductive via connected to the first electrode (“CM1 may be electrically connected to the second electrode E2 of the storage capacitor SC” ¶ [0087]), a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via, and the drain electrode comprises a third conductive via (“a connecting member CM1 and a connecting member CM2 respectively connected to the drain electrode D1 and the source electrode S1 through contact holes H1 and H2 formed in the fourth insulating layer 161,” ¶ [0086]) connected to the channel layer and a second circuit layer connected to the third conductive via.
However, SON et al. does not disclose, a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via, and a third conductive via connected to the channel layer and a second circuit layer connected to the third conductive via.
In the similar field of endeavor of TFT transistors, CHO et al. Fig. 3 discloses, a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via (“the connection electrode 150 can be electrically connected to the third drain electrode 333 of the third thin-film transistor 330. In addition, the connection electrode 150 can be electrically connected to the second capacitor electrode 142 of the storage capacitor 140 through the contact hole formed” ¶ [0083]), and a third conductive via connected to the channel layer and a second circuit layer connected to the third conductive via (“the third source electrode 332 and the third drain electrode 333 of the third thin-film transistor 330 can be connected to the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116. Thus, the third source electrode 332 of the third thin-film transistor 330 can be connected to the third source region 331b of the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116, and the third drain electrode 333 of the third thin-film transistor 330 can be connected to the third drain region 331c of the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116.” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify contact vias of SON et al. with the contact vias of CHO et al. in order to provide a display apparatus that is capable of differently implementing the characteristics of thin-film transistors by differently configuring the structure of a gate electrode, the structure of an insulating layer on the gate electrode or the structure of a source and a drain, based on the location and the characteristics of the transistor. (CHO et al., ¶ [0009]).
Regarding Claim 20, SON et al. discloses the limitations of claim 1. SON et al. further discloses, wherein the source electrode comprises a first conductive via connected to the first electrode (“CM1 may be electrically connected to the second electrode E2 of the storage capacitor SC” ¶ [0087]), a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via, and the drain electrode comprises a third conductive via (“a connecting member CM1 and a connecting member CM2 respectively connected to the drain electrode D1 and the source electrode S1 through contact holes H1 and H2 formed in the fourth insulating layer 161,” ¶ [0086]) connected to the channel layer and a second circuit layer connected to the third conductive via.
However, SON et al. does not disclose, a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via, and a third conductive via connected to the channel layer and a second circuit layer connected to the third conductive via.
In the similar field of endeavor of TFT transistors, CHO et al. Fig. 3 discloses, a second conductive via connected to the channel layer and a first circuit layer connecting the first conductive via and the second conductive via (“the connection electrode 150 can be electrically connected to the third drain electrode 333 of the third thin-film transistor 330. In addition, the connection electrode 150 can be electrically connected to the second capacitor electrode 142 of the storage capacitor 140 through the contact hole formed” ¶ [0083]), and a third conductive via connected to the channel layer and a second circuit layer connected to the third conductive via (“the third source electrode 332 and the third drain electrode 333 of the third thin-film transistor 330 can be connected to the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116. Thus, the third source electrode 332 of the third thin-film transistor 330 can be connected to the third source region 331b of the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116, and the third drain electrode 333 of the third thin-film transistor 330 can be connected to the third drain region 331c of the third active layer 331 through the contact hole formed in the second interlayer insulating layer 116.” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify contact vias of SON et al. with the contact vias of CHO et al. in order to provide a display apparatus that is capable of differently implementing the characteristics of thin-film transistors by differently configuring the structure of a gate electrode, the structure of an insulating layer on the gate electrode or the structure of a source and a drain, based on the location and the characteristics of the transistor. (CHO et al., ¶ [0009]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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