winterssDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 in the reply filed on 02/20/2026 is acknowledged.
Claims 16-20 are now canceled; Claims 21-25 are newly-added.
Claims 1-15 and 21-25 have been fully considered in Examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informalities:
Claim 15, lines 1-2: “wherein: the two-dimensional array of third semiconductor dies including arrays of third top metal bonding pads” should read --- wherein: the two-dimensional array of third semiconductor dies includes arrays of third top metal bonding pads ---
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PG Pub No US2021/0066251A1).
Regarding claim 1, Kim teaches a method [see figs. 4-8, 0099, 0119] of forming a semiconductor structure (10) fig. 1B [0128, 0133], the method comprising:
providing a first wafer (Wa) fig. 8 [0119] (refer to exemplary structure W in fig. 4 [0101]) including a two-dimensional array (at least two-dimensional in zx plane, with two C1 chips shown) [0101] of first semiconductor dies (C1) fig. 4 [0101, 0119] (see also fig. 1B) including arrays of first top metal bonding pads (comprising 122 with 243) fig. 1B [0038, 0053] (see also fig. 4) and arrays of first bottom metal bonding pads (comprising 124) fig. 1B [0038, 0047];
providing a second wafer (Wb) fig. 8 [0119] including a two-dimensional array of second semiconductor dies (C2) fig. 1b [0036, 0101, 0119] (Wb comprises a plurality of dies C2 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including arrays of second top metal bonding pads (222 with 343) fig. 1B [0053, 0056] and arrays of second bottom metal bonding pads (224 with 241) fig. 1B [0053];
bonding the second wafer (Wb) fig. 8a [0119] to the first wafer (Wa) fig. 8a [0119] by performing a first metal-to-metal bonding process (TCB) [0116, 0119] in which the arrays of first top metal bonding pads (comprising 122 with 243) fig. 1B [0038, 0053] are bonded to the arrays of second bottom metal bonding pads (224 with 241) fig. 1B [0053] through first intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]);
providing a third wafer (Wc) fig. 8 [0119] including a two-dimensional array of third semiconductor dies (C3) fig. 1b [0036, 0101, 0119] (Wc comprises a plurality of dies C3 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including arrays of third bottom metal bonding pads (comprising 324 with 341) fig. 1B [0054]; and
bonding the third wafer (Wc) fig. 8a [0119] to the second wafer (Wb) fig. 8a [0119] by performing a second metal-to-metal bonding process (TCB) [0116, 0119] in which the arrays of second top metal bonding pads (222 with 343) fig. 1B [0053, 0056] are bonded to the arrays of third bottom metal bonding pads (comprising 324 with 341) fig. 1B [0054] through second intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047, 0056] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]);.
Regarding claim 7, Kim teaches the method [see figs. 4-8, 0099, 0119] of claim 1. Kim also teaches comprising dicing a bonded assembly comprising the first wafer (Wa) fig. 8a [0119], the second wafer (Wb) fig. 8a [0119], and the third wafer (Wa) fig. 8a [0119] into a plurality of composite packages (10) fig. 1B [0036] comprising an assembly of a respective one of the first semiconductor dies (C1) fig. 1B [0037, 0118-0119], a respective one of the second semiconductor dies (C2) fig. 1B [0037], and a respective one of the third semiconductor dies (C3) fig. 1B [0037] (wafers Wa-Wd comprising dies/chips [0118] bonded, then diced into individual packages in embodiment of fig. 8A [0118-0119]).
Regarding claim 8, Kim teaches the method [see figs. 4-8, 0099, 0119] of claim 7. Kim also teaches wherein the plurality of composite packages (10) fig. 1B [0036, 0119] comprise a respective additional one of the third semiconductor dies (C4 atop C3) fig. [0036].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2021/0066251A1), as applied in claim 1 above, in view of Yu (U.S. PG Pub No US2022/0223530A1).
Regarding claim 2, Kim teaches the method [see figs. 4-8, 0099, 0119] of claim 1. However, Kim does not explicitly disclose wherein the third wafer (Wc) fig. 8a [0119] comprises a reconstituted wafer in which third semiconductor dies (C3) fig. 1B [0037] of the array of third semiconductor dies (C3) are laterally surrounded by a molding compound matrix.
Yu teaches a method [0036] for forming a package (100) fig. 1A [0018] wherein the third wafer (tier-3) fig. 1A [0018] comprises a reconstituted wafer [0050] in which third semiconductor dies (20C) fig. 1A [0023] of the array (see fig. 1B for array configuration [0026]) of third semiconductor dies (20C) are laterally surrounded by a molding compound matrix (collective 134 material) fig. 1A [0018, 0049].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to include the formation of molding/encapsulant material [0049] laterally surrounding the array of dies [0018] in order to structurally-reconstituted the wafer(s) [0050-0053] and enable the formation of additional circuitry in the molding material [0035] that enhances electrical interconnections with the dies [0035], as taught by Yu.
Regarding claim 3, Kim in view of Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 2. However, Kim does not explicitly disclose wherein the second wafer (Wb) fig. 8a [0119] comprises an additional reconstituted wafer in which second semiconductor dies (C2) fig. 1B [0037] of the array of second semiconductor dies are laterally surrounded by an additional molding compound matrix.
Yu teaches a method [0036] for forming a package (100) fig. 1A [0018] wherein the second wafer (tier-2) fig. 1A [0018] comprises an additional reconstituted wafer [0050] in which second semiconductor dies (20B) fig. 1A [0023] of the array (see fig. 1B for array configuration [0026]) of second semiconductor dies (20B) are laterally surrounded by an additional molding compound matrix (collective 132 material) fig. 1A [0018, 0049].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to include the formation of molding/encapsulant material [0049] laterally surrounding the array of dies [0018] in order to structurally-reconstituted the wafer(s) [0050-0053] and enable the formation of additional circuitry in the molding material [0035] that enhances electrical interconnections with the dies [0035], as taught by Yu.
Regarding claim 4, Kim in view of Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 3. Kim also teaches wherein each of the first semiconductor dies (C1) fig. 4 [0037] comprises a respective portion (portion of 110 laterally between adjacent 125s) fig. 4 [0038] of a semiconductor substrate (110) fig. 4 [0038] that continuously extends over an entire area (area of portion of 100, laterally between adjacent 125s, underlying respective portion of 110) fig. 4 [0038] of the first wafer (W1 comprising 100) [0038, 0119].
However, Kim does not explicitly disclose wherein the first semiconductor dies (C1s) are interconnected to one another.
Yu teaches a method [0036] for forming a package (100) fig. 15C [0062, 0018] wherein the first semiconductor dies (lower MD1’s) fig. 15C [0062] are interconnected to one another (by redistribution layer 50) fig. 15C [0050].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to interconnect the array lowermost, first dies [0023, 0062] in order to allow for the exchange and cooperation of neighboring dies [0035-0036, 0062] so as to enhance the integration of dies in the package [0002, 0070] for improved computing efficiency [0002, 0070] and reduced energy consumption [0002], as taught by Yu.
Regarding claim 5, Kim in view of Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 3. However, Kim does not explicitly disclose wherein the first wafer (Wa) fig. 8a [0119] comprises another additional reconstituted wafer in which the first semiconductor dies (C1) fig. 1B [0037] are laterally surrounded by another additional molding compound matrix.
Yu teaches a method [0036] for forming a package (100) fig. 1A [0018] wherein the first wafer (tier-1) fig. 1A [0018] comprises another additional reconstituted wafer [0050] in which first semiconductor dies (20A) fig. 1A [0023] are laterally surrounded by an another additional molding compound matrix (collective 130 material) fig. 1A [0018, 0049].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to include the formation of molding/encapsulant material [0049] laterally surrounding the array of dies [0018] in order to structurally-reconstituted the wafer(s) [0050-0053] and enable the formation of additional circuitry in the molding material [0035] that enhances electrical interconnections with the dies [0035], as taught by Yu.
Regarding claim 6, Kim teaches the method [see figs. 4-8, 0099, 0119] of claim 1. However, Kim does not explicitly disclose wherein:
the third semiconductor dies (C3) fig. 1B [0037] comprises first-type semiconductor dies and second-type semiconductor dies (multiple C3 die types not shown); and
the two-dimensional array of third semiconductor dies (C3) comprises a two-dimensional periodic array of a repletion unit that includes a combination of a first-type semiconductor die and a second-type semiconductor die that is different from the first-type semiconductor die.
Yu teaches a method [0036] for forming a package (100) fig. 15C [0018, 0060] wherein:
the third semiconductor dies (LD of tier 2, above lower pair of MD1’s) fig. 15C [0062] comprises first-type semiconductor dies (right LD may be first type of logic die) fig. 15C [0020-0021] and second-type semiconductor dies (left LD may be of second, different type of logic die) fig. 15C [0020-0021]; and
the two-dimensional array (see fig. 1B for array configuration [0026]) of third semiconductor dies (LDs) comprises a two-dimensional periodic array of a repletion unit (vertically-repeating units in up/down direction of plan view of fig. 1B) that includes a combination of a first-type semiconductor die (right LD may be first type of logic die) and a second-type semiconductor die (left LD may be of second, different type of logic die) that is different from the first-type semiconductor die (right LD).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim such that the plurality of third dies of a single tier [0062] comprise a plurality of different types of logic dies [0020-0021] in order to enhance the integration density of multiple types of dies in a single package [0002, 0029, 0070] while maintaining high computing efficiency [0002, 0070] and low energy consumption [0002], as taught by Yu.
Claims 9-11, 15, 21-22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2021/0066251A1) in view of Liao (U.S. PG Pub No US2020/0098736A1).
Regarding claim 9, Kim teaches a method [see figs. 4-8, 0099, 0119] of forming a semiconductor structure (10) fig. 1B [0128, 0133], the method comprising:
attaching a first wafer (Wa) fig. 8 [0119] (refer to exemplary structure W in fig. 4 [0101]) including a two-dimensional array (at least two-dimensional in zx plane, with two C1 chips shown) [0101] of first semiconductor dies (C1) fig. 4 [0101, 0119] (see also fig. 1B) including arrays of first top metal bonding pads (comprising 122 with 243) fig. 1B [0038, 0053] (see also fig. 4) and arrays of first bottom metal bonding pads (comprising 124) fig. 1B [0038, 0047] (attaching first wafer Wa to wafer Wb [see fig. 8a, 0119];
attaching a second wafer (Wb) fig. 8 [0119] including a two-dimensional array of second semiconductor dies (C2) fig. 1b [0036, 0101, 0119] (Wb comprises a plurality of dies C2 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including arrays of second top metal bonding pads (222 with 343) fig. 1B [0053, 0056] and arrays of second bottom metal bonding pads (224 with 241) fig. 1B [0053] to the first wafer (Wa) [see fig. 8, 0119] by performing a first metal-to-metal bonding process (TCB) [0116, 0119] in which the arrays of first top metal bonding pads (comprising 122 with 243) fig. 1B [0038, 0053] are bonded to the arrays of second bottom metal bonding pads (224 with 241) fig. 1B [0053] through first intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]);
attaching a third wafer (Wc) fig. 8a [0119] including a two-dimensional array of third semiconductor dies (C3) fig. 1b [0036, 0101, 0119] (Wc comprises a plurality of dies C3 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including arrays of third bottom metal bonding pads (comprising 324 with 341) fig. 1B [0054] to the second wafer (Wb) [see fig. 8a, 0119] by performing a second metal-to-metal bonding process (TCB) [0116, 0119] in which the arrays of second top metal bonding pads (222 with 343) fig. 1B [0053, 0056] are bonded to the arrays of third bottom metal bonding pads (comprising 324 with 341) fig. 1B [0054] through second intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047, 0056] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]).
However, Kim does not explicitly disclose attaching the first wafer (Wa) fig. 8 [0119] to a top surface of a first carrier wafer (carrier wafer not explicitly disclosed).
Liao teaches a method [see figs. 2A-2K, 0029] comprising attaching the first wafer (A1 comprising 100a with 200a) fig. 2A [0029, 0027] to a top surface of a first carrier wafer (C1) fig. 2A [0029].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to utilize a carrier substrate under the first wafer die-stack [0029, 0027] in order to support the first wafer [0029] and providing more control over subsequent processing operations [0042], such enabling flipping of the wafer(s) [0042], as taught by Liao.
Regarding claim 10, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 9. Kim in view of Liao (with reference to Liao) also teaches further comprising:
attaching a second carrier wafer (C2) fig. 2I [0042] to a top surface (shown as upper periphery of 702 in fig. 2H) fig. 2H [0042] of a bonded assembly (package of fig. 2H) comprising the first carrier wafer (C1) fig. 2H [0029], the first wafer (100a with 200a) fig. 2H [0029], the second wafer (100b with 200b) fig. 2H [0034], and the third wafer (100c with 200c) fig. 2H [0038]; and
detaching the first carrier wafer (C1) from the first wafer (comprising 100a) after attaching [0042] the second carrier wafer (C2) to the bonded assembly [0042].
Regarding claim 11, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 10. Kim also teaches further comprising:
attaching arrays of solder material portions (141) fig. 1B [0047-0050] (see formation of 141 in fig. 5 [0099]) to the arrays of first bottom metal bonding pads (comprising 124) fig. 1B [0038, 0047]; and
dicing the bonded assembly comprising the first wafer (Wa) fig. 8a [0119], the second wafer (Wb) fig. 8a [0119], and the third wafer (Wa) fig. 8a [0119] into a plurality of composite packages (10) fig. 1B [0036] comprising a vertical stack of a respective one of the first semiconductor dies (C1) fig. 1B [0037, 0118-0119], a respective one of the second semiconductor dies (C2) fig. 1B [0037], and a respective one of the third semiconductor dies (C3) fig. 1B [0037] (wafers Wa-Wd comprising dies/chips [0118] bonded, then diced into individual packages in embodiment of fig. 8A [0118-0119]).
Regarding claim 15, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 9. Kim also teaches wherein:
the two-dimensional array of third semiconductor dies (C3) fig. 1B [0036, 0101, 0119] includes arrays of third top metal bonding pads (322 with 443) fig. 1B [0056]; and
the method comprises attaching a fourth wafer (W4) fig. 8A [0118-0119] comprising a two-dimensional array of fourth semiconductor dies (C4) fig. 8A [0037, 0118] including arrays of fourth bottom metal bonding pads (comprising 441) fig. 1B [0055-0056] to the third wafer (W3) by performing a third metal-to-metal bonding process (TCB) [0116, 0119] in which the arrays of third top metal bonding pads (322 with 443) fig. 1B [0056] are bonded to the arrays of fourth bottom metal bonding pads (comprising 441) fig. 1B [0055-0056] through second intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047, 0056] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]).
Regarding claim 21, Kim teaches a method [see figs. 4-8, 0099, 0119] of forming a semiconductor structure (10) fig. 1B [0128, 0133], the method comprising:
attaching a first wafer (Wa) fig. 8 [0119] (refer to exemplary structure W in fig. 4 [0101]) including a two-dimensional array (at least two-dimensional in zx plane, with two C1 chips shown) [0101] of first semiconductor dies (C1) fig. 4 [0101, 0119] (see also fig. 1B) including first metal bonding pads (comprising 122 with 243) fig. 1B [0038, 0053] (see also fig. 4) (attaching first wafer Wa to wafer Wb [see fig. 8a, 0119];
attaching a second wafer (Wb) fig. 8 [0119] including a two-dimensional array of second semiconductor dies (C2) fig. 1b [0036, 0101, 0119] (Wb comprises a plurality of dies C2 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including second metal bonding pads (comprising 222 with 343 and 224 with 241) fig. 1B [0053, 0056] to the first wafer (Wa) [see fig. 8, 0119] by bonding (though TCB process) [0116, 0119] a (top) portion of the first metal bonding pads (comprising 243) to a (bottom) portion of the second metal bonding pads (comprising 241) (lower x-41 layers are bonded to upper x-43 layers [0047, 0116, 0119]);
attaching a third wafer (Wc) fig. 8 [0119] including a two-dimensional array of third semiconductor dies (C3) fig. 1b [0036, 0101, 0119] (Wc comprises a plurality of dies C3 in array similar to C1’s of W in fig. 4, prior to the individual dicing step shown in fig. 8a [0119]) including third metal bonding pads (comprising 324 with 341 and 322 with 443) fig. 1B [0054-0055] to the second wafer (Wb) [see fig. 8a, 0119] by bonding another (top) portion of the second metal bonding pads (comprising 341) to a (bottom) portion of the third metal bonding pads (comprising 343) (lower x-41 layers are bonded to upper x-43 layers [0047, 0116, 0119]).
However, Kim does not explicitly disclose attaching the first wafer (Wa) fig. 8 [0119] to a top surface of a first carrier wafer (carrier wafer not explicitly disclosed).
Liao teaches a method [see figs. 2A-2K, 0029] comprising attaching the first wafer (A1 comprising 100a with 200a) fig. 2A [0029, 0027] to a top surface of a first carrier wafer (C1) fig. 2A [0029].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to utilize a carrier substrate under the first wafer die-stack [0029, 0027] in order to support the first wafer [0029] and providing more control over subsequent processing operations [0042], such enabling flipping of the wafer(s) [0042], as taught by Liao.
Regarding claim 22, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 21. Kim also teaches wherein:
bonding the second wafer (Wb) fig. 8A [0119] to the first wafer (Wa) fig. 8A [0119] comprises performing a first metal-to-metal bonding process in which the (top) portion of the first metal bonding pads (comprising 243) fig. 1B [0038, 0053] is bonded to the (bottom) portion of the second metal bonding pads (comprising 241) fig. 1B [0053, 0056] through first intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]); and
bonding the third wafer (Wc) fig. 8A [0119] to the second wafer (Wb) fig. 8A [0119] comprises performing a second metal-to-metal bonding process in which the another (top) portion of the second metal bonding pads (comprising 343) fig. 1B [0054-0055]is bonded to the portion of the third metal bonding pads (comprising 341) fig. 1B [0054-0055] through second intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]).
Claims 12-14 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2021/0066251A1) modified by Liao (U.S. PG Pub No US2020/0098736A1), as applied in claims 9 and 15 above, and further in view of Yu (U.S. PG Pub No US2022/0223530A1).
Regarding claim 12, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 9. However, Kim does not explicitly disclose wherein one of the first wafer (Wa) fig. 8A [0119], the second wafer (Wb) fig. 8A [0119], or the third wafer (Wc) fig. 8A [0119] comprises a reconstituted wafer in which a molding compound matrix laterally surrounds the first semiconductor dies (C1) fig. 1B [0037], the second semiconductor dies (C2) fig. 1B [0037], or the third semiconductor dies (C3) fig. 1B [0037].
Yu teaches a method [0036] for forming a package (100) fig. 1A [0018] wherein the third wafer (tier-3) fig. 1A [0018] comprises a reconstituted wafer [0050] in which a molding compound matrix (collective 134 material) fig. 1A [0018, 0049] (see fig. 1B for matrix-array configuration [0026]) laterally surrounds the third semiconductor dies (20C) fig. 1A [0023].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to include the formation of molding/encapsulant material [0049] laterally surrounding the array of dies [0018] in order to structurally-reconstituted the wafer(s) [0050-0053] and enable the formation of additional circuitry in the molding material [0035] that enhances electrical interconnections with the dies [0035], as taught by Yu.
Regarding claim 13, Kim in view of Liao and Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 12. Kim in view of Liao and Yu (with reference to Yu) also teaches wherein another of the second wafer (tier-2) fig. 1A [0018] comprises an additional reconstituted wafer [0050] comprising an additional molding compound matrix (collective 132 material) fig. 1A [0018, 0049] (see fig. 1B for matrix-array configuration [0026]).
Regarding claim 14, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 9. However, Kim does not explicitly disclose wherein:
the third semiconductor dies (C3) fig. 1B [0037] comprises first-type semiconductor dies and second-type semiconductor dies (multiple C3 die types not shown); and
the third wafer (W3) fig. 8A [0119] comprises a two-dimensional periodic array of a repletion unit that includes a combination of a first-type semiconductor die and a second-type semiconductor die that is different from the first-type semiconductor die.
Yu teaches a method [0036] for forming a package (100) fig. 15C [0018, 0060] wherein:
the third semiconductor dies (LD of tier 2, above lower pair of MD1’s) fig. 15C [0062] comprises first-type semiconductor dies (right LD may be first type of logic die) fig. 15C [0020-0021] and second-type semiconductor dies (left LD may be of second, different type of logic die) fig. 15C [0020-0021]; and
the third wafer (comprising LDs) comprises a two-dimensional periodic array (see fig. 1B for array configuration [0026]) of a repletion unit (vertically-repeating units in up/down direction of plan view of fig. 1B) that includes a combination of a first-type semiconductor die (right LD may be first type of logic die) and a second-type semiconductor die (left LD may be of second, different type of logic die) that is different from the first-type semiconductor die (right LD).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim such that the plurality of third dies of a single tier [0062] comprise a plurality of different types of logic dies [0020-0021] in order to enhance the integration density of multiple types of dies in a single package [0002, 0029, 0070] while maintaining high computing efficiency [0002, 0070] and low energy consumption [0002], as taught by Yu.
Regarding claim 23, Kim in view of Liao teaches the method [see figs. 4-8, 0099, 0119] of claim 22. However, Kim does not explicitly disclose wherein one of the first wafer (Wa) fig. 8A [0119], the second wafer (Wb) fig. 8A [0119], or the third wafer (Wc) fig. 8A [0119] comprises a reconstituted wafer in which a molding compound matrix laterally surrounds a first two-dimensional array selected from the two-dimensional array the first semiconductor dies (C1) fig. 1B [0037], the second semiconductor dies (C2) fig. 1B [0037], or the third semiconductor dies (C3) fig. 1B [0037].
Yu teaches a method [0036] for forming a package (100) fig. 1A [0018] wherein the third wafer (tier-3) fig. 1A [0018] comprises a reconstituted wafer [0050] in which a molding compound matrix (collective 134 material) fig. 1A [0018, 0049] laterally surrounds laterally surrounds a first two-dimensional array selected from the two-dimensional array (see fig. 1B for matrix-array configuration [0026]) the third semiconductor dies (20C) fig. 1A [0023].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim to include the formation of molding/encapsulant material [0049] laterally surrounding the array of dies [0018] in order to structurally-reconstituted the wafer(s) [0050-0053] and enable the formation of additional circuitry in the molding material [0035] that enhances electrical interconnections with the dies [0035], as taught by Yu.
Regarding claim 24, Kim in view of Liao and Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 23. However, Kim does not explicitly disclose wherein:
the third semiconductor dies (C3) fig. 1B [0037] comprises first-type semiconductor dies and second-type semiconductor dies (multiple C3 die types not shown); and
the two-dimensional array of third semiconductor dies (C3) comprises a two-dimensional periodic array of a repletion unit that includes a combination of a first-type semiconductor die and a second-type semiconductor die that is different from the first-type semiconductor die.
Yu teaches a method [0036] for forming a package (100) fig. 15C [0018, 0060] wherein:
the third semiconductor dies (LD of tier 2, above lower pair of MD1’s) fig. 15C [0062] comprises first-type semiconductor dies (right LD may be first type of logic die) fig. 15C [0020-0021] and second-type semiconductor dies (left LD may be of second, different type of logic die) fig. 15C [0020-0021]; and
the two-dimensional array (see fig. 1B for array configuration [0026]) of third semiconductor dies (LDs) comprises a two-dimensional periodic array of a repletion unit (vertically-repeating units in up/down direction of plan view of fig. 1B) that includes a combination of a first-type semiconductor die (right LD may be first type of logic die) and a second-type semiconductor die (left LD may be of second, different type of logic die) that is different from the first-type semiconductor die (right LD).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim such that the plurality of third dies of a single tier [0062] comprise a plurality of different types of logic dies [0020-0021] in order to enhance the integration density of multiple types of dies in a single package [0002, 0029, 0070] while maintaining high computing efficiency [0002, 0070] and low energy consumption [0002], as taught by Yu.
Regarding claim 25, Kim in view of Liao and Yu teaches the method [see figs. 4-8, 0099, 0119] of claim 23. Kim also teaches wherein:
the two-dimensional array of third semiconductor dies (C3) fig. 1B [0036, 0101, 0119] includes arrays of third top metal bonding pads (322 with 443) fig. 1B [0056]; and
the method further comprises attaching a fourth wafer (Wd) fig. 8a [0119] comprising a two-dimensional array of fourth semiconductor dies (C4) [0037] including arrays of fourth bottom metal bonding pads (comprising 441) fig. 1B [0055-0056] to the third wafer (Wc) by performing a third metal-to-metal bonding process in which the arrays of third top metal bonding pads (comprising 443) are bonded to the arrays of fourth bottom metal bonding pads (comprising 441) through third intermetallic diffusion (lower x-41 layers are bonded to upper x-43 layers [0047] by intermetallic-diffusion [0047], as evidenced by the formation of intermediate metal layer formed by combined, diffused metal species therebetween [0051]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature multi-tiered stacks of bonded semiconductor dies.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 03/14/2026
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