DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 21 November 2023. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8, 9, 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa et al. (U.S. Patent Application Publication 2015/0293384).
Referring to Claim 1, Ogawa teaches in Fig. 1 and 2 (par. 36-43 and 105) a semiconductor device, comprising: a waveguide (12) over a first dielectric layer (substrate 1 may be an insulator; or an SOI where the lower cladding layer 2 is a buried oxide; par. 38-40), wherein: the waveguide comprises a first portion (one end portion of 22; Fig. 2), a second portion (central portion of 22; Fig. 2), and a third portion (another end portion of 22; Fig. 2), and the second portion (central portion of 22) is between the first portion (one end portion of 22) and the third portion (another end portion of 22); a first doped semiconductor structure (6; par. 43, 50 and 55) contacting a first sidewall of the second portion (central portion of 22); and a second doped semiconductor structure (5; par. 43, 50 and 55) contacting a second sidewall of the second portion (central portion of 22) opposite the first sidewall such that the second portion of the waveguide (central portion of 22) is between the first doped semiconductor structure (6) and the second doped semiconductor structure (5).
Referring to Claim 2, Ogawa further teaches wherein: the first doped semiconductor structure (6) is an n-doped semiconductor structure, and the second doped semiconductor structure (5) is a p-doped semiconductor structure (par. 50 and 55).
Referring to Claim 3, Ogawa further teaches a second dielectric layer (7), wherein: the second dielectric layer (7) is spaced apart from the first sidewall (interface between 6 and 4b) of the second portion (central portion of 22) by the first doped semiconductor structure (6), and the second dielectric layer (7) is spaced apart from the second sidewall (interface between 5 and 3b) of the second portion (central portion of 22) by the second doped semiconductor structure (5).
Referring to Claim 4, Ogawa further teaches wherein the second dielectric layer (7) is in contact with a sidewall (of 3a and 4a) and a top surface (of 3 and 4) of the first portion (one end portion of 22) of the waveguide.
Referring to Claim 5, Ogawa further teaches wherein the second dielectric layer (7) is in contact with a top surface (of 3 and 4) of the second portion (central portion of 22) of the waveguide.
Referring to Claim 8, Ogawa further teaches wherein: the first doped semiconductor structure (6) is an n-doped semiconductor structure, and the second portion of the waveguide comprises an n-doped region (4) adjacent the n-doped semiconductor structure (6) (par. 43).
Referring to Claim 9, Ogawa further teaches wherein a concentration of dopants in the n-doped region (4) is less than a concentration of dopants in the n-doped semiconductor structure (6) (par. 55).
Referring to Claim 11, Ogawa further teaches wherein: the second doped semiconductor structure (5) is a p-doped semiconductor structure, and the second portion of the waveguide comprises a p-doped region (3) adjacent the p-doped semiconductor structure (5) (par. 43).
Referring to Claim 12, Ogawa further teaches wherein the second portion of the waveguide comprises a depletion region (13; inherent to the PN junction) between the n-doped region (4) and the p- doped region (3).
Claims 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu et al. (U.S. Patent Application Publication 2012/0189239).
Referring to Claim 13, teaches in Fig. 8 a method for forming a semiconductor device, comprising: forming a patterned semiconductor layer (804) over a first dielectric layer (803); forming a first patterned photoresist (805) over the patterned semiconductor layer (804), wherein the first patterned photoresist (805) defines a first opening (806) exposing a first portion of the patterned semiconductor layer (804); doping the first portion of the patterned semiconductor layer (804) through the first opening (806) to form a first doped semiconductor structure (814/854); forming a second patterned photoresist (820) over the patterned semiconductor layer (804) after doping the first portion of the patterned semiconductor layer (804), wherein the second patterned photoresist (820) defines a second opening (822) exposing a second portion of the patterned semiconductor layer (804); and doping the second portion of the patterned semiconductor layer (804) through the second opening (822) to form a second doped semiconductor structure (828/868).
Referring to Claim 14 Tu further teaches wherein a third portion (832) of the patterned semiconductor layer (804) between the first portion of the patterned semiconductor layer (804) and the second portion of the patterned semiconductor layer (832) is concealed by both the first patterned photoresist (805) and the second patterned photoresist (820).
Referring to Claim 15, Tu further teaches wherein at least a portion of the patterned semiconductor layer (804) defines a waveguide (par. 2, 9, 10, 98, 99, 105, 106, 129).
Referring to Claim 16, Tu further teaches forming a third patterned photoresist (846) over the patterned semiconductor layer (804) after doping the second portion of the patterned semiconductor layer (804), wherein the third patterned photoresist (846) defines a third opening exposing a third portion of the patterned semiconductor layer (804); and doping the third portion of the patterned semiconductor layer (804) through the third opening to form a first doped region (852), wherein the first doped region (852) is between the first doped semiconductor structure (814/854) and the second doped semiconductor structure (828).
Referring to Claim 17, Tu further teaches forming a fourth patterned photoresist (860) over the patterned semiconductor layer (804) after doping the third portion of the patterned semiconductor layer (804), wherein the fourth patterned photoresist (860) defines a fourth opening exposing a fourth portion of the patterned semiconductor layer (804); and doping the fourth portion of the patterned semiconductor layer (804) through the fourth opening to form a second doped region (866), wherein the second doped region (866) is between the first doped region (852) and the second doped semiconductor structure (828/868).
Allowable Subject Matter
Claims 6, 7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 6, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the second dielectric layer is in contact with the first dielectric layer in combination with all of the limitations of Claim 1, 3 and 6.
Regarding Claim 7, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device comprising: a second dielectric layer overlying the waveguide and contacting the first dielectric layer in combination with all of the limitations of Claim 1 and 7.
Regarding Claim 10, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor wherein a concentration of dopants in the n-doped region changes in a direction extending from a top surface of the n-doped region to a bottom surface of the n-doped region in combination with all of the limitations of Claim 1, 8 and 10.
Regarding Claim 18, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising: the first dielectric layer and a top surface of the second portion of the waveguide are in contact with the second dielectric layer in combination with all of the limitations of Claim 18. Claims 19 and 20 include the limitations of claim 18.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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