Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7 and 9-11 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Rajagopalan (US 2016/0231269)
Regarding claim 1, the prior art discloses:
A method comprising:
generating first specification data of a semiconductor device (specification of IC/semiconductor/die/electronic circuits/ device (par 18, 36, 39, 48, 75-77));
performing, to the first specification data, a first evaluation operation corresponding to a first physical feature to the first specification data, to generate first parameters;(fig 4-5, 7-8 and related text, i.e., simulate/ evaluate/ analyze/ weight / score/ rank/ estimate one of lengths, widths, regions, fingers, circuits, area components, to produce first parameters/ values/ ranges/ scores);
performing, to the first specification data, a second evaluation operation corresponding to a second physical feature different from the first physical feature, to generate second parameters
(fig 4-5, 7-8 and related text, i.e., the loop/ iteration process in these figures preform a second simulate/ evaluate/ analyze/ weight / score/ rank/ estimate another different one of lengths, widths, regions, fingers, circuits, components to produce/generate second parameters/ values/ range/ scores);
comparing the first and the second parameters with preset parameters (fig 4-5, 7-8 and related text, i.e., compare/match parameters with i.e., specification/region criteria, permitted ranges, ideal/target values, target limit/ criteria, boundary limit, acceptable values/parameters); and
when the first and the second parameters meet the preset parameters , manufacturing the semiconductor device according to the first specification data (fig 4-5, 7-8 and related text, i.e., meets/acceptable the area target criteria / region criteria, matching matrix provides a probabilistic framework to match parameters, satisfy the specification criteria, then inherently manufacturing. For Applicant information, GDS file is for manufacturing.
Claim 9 recite similar subject matter and rejected for the same reason. For simultaneous operations, see one or more of dynamic weights of the parameter values, massively parallel processing of designs (e.g., circuit simulation, circuit verification, circuit test, etc.), optimization processes may be conducted sequentially or in parallel (e.g., concurrently or simultaneously), running any combination of the analysis modules simultaneously, as disclosed in the prior art
(claim 2) when the first parameters and the second parameters do not meet the preset parameters, adjusting the first specification data to generate second specification data; and after the first specification data is adjusted, generating the first parameters and the second parameters based on the second specification data. (fig 4-5, 7-8 and related text, i.e., if parameter vales exceeds parameter ranges, not acceptable, not within target/limit, not match, not within performance/ specification , specification/region is not met , then, i.e., weight may be increased by a factor, modifying/adjust a circuit design to achieve all electrical specification criterion/target, adjust weights/parameter to provide values of electrical specification criteria/target/limit, to meet/satisfy specification, and/or modified scripts and netlists are presented to the electrical simulator which returns the values for the specifications for each candidate solution, etc. After the specification is changed/adjusted/modified, the loop/iteration process in fig 4-5, 7-8 repeat simulate/ evaluate/ analyze/ weight / score/ rank/ estimate/compare/match process to generate optimized/ subsequent parameters/values based on the optimized/ altered/ adjusted/ changed/modified specification
(Claim 3) selecting the first evaluation operation and second first evaluation operation from a plurality of evaluation operations according to the first specification data ( the loop/iteration process in fig 4-5, 7-8 repeat simulate/ evaluate/ analyze/ weight / score/ rank/ estimate/compare/match process for best/fit/optimized/target/ideal/acceptable/satisfied parameters/ values/ specification)
(Claim 4) when the first specification data includes data corresponding to a third physical feature, selecting a third evaluation operation corresponding to the third physical feature from the plurality of evaluation operations; when the third evaluation operation is selected, performing the third evaluation operation to the first specification data, to generate third parameters; comparing the first parameters, the second parameters and the third parameters with the preset parameters; and when the first parameters, the second parameters and the third parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data (the loop/iteration process in fig 4-5, 7-8 repeat simulate/ evaluate/ analyze/ weight / score/ rank/ estimate/ compare/match process for best/fit/optimized/target/ideal/acceptable/satisfied parameters/ values/ specification)
(Claim 5) wherein when the first specification data does not include the data associated with the third physical feature, the third evaluation operation is not performed data (the loop/iteration process in fig 4-5, 7-8 repeat simulate/ evaluate/ analyze/ weight / score/ rank/ estimate/ compare/match process for best/fit/optimized/target/ideal/acceptable/satisfied parameters/ values/ specification. The physical feature and/or simulate/ evaluate/ analyze/ weight / score/ rank/ estimate/ compare/match operation not fit/match, not within /satisfy rank/score/weight/limit/performance/target/ranged is not used/excluded and the process in fig 4-5, 7-8 repeat)
(Claim 7) extracting ( the loop/iteration process in fig 4-5, 7-8 feedback/extract/derive data/values/parameters) first physical data and second physical data from the first specification data; comparing the first physical data with preset element parameters; when the first physical data do not meet the preset element parameters, adjusting the first specification data; and when the first physical data meets the preset element parameters, generating the first parameters according to the first physical data and the second physical data, wherein the first physical data is different from the second physical data (fig 4-5, 7-8 and related text)
Claims 10-11 recite similar subject matter and are rejected for the same reason.
Claims 1-7, 9-12, 14-15 and 17-18 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Arp (US 2017/0161423)
Regarding claim 1, the prior art discloses:
A methos comprising:
generating first specification data of a semiconductor device (see one or more of par 20-22, 34, 38-41);
performing, to the first specification data, a first evaluation operation corresponding to a first physical feature to the first specification data, to generate first parameters (fig 5-7 and related text);
performing, to the first specification data, a second evaluation operation corresponding to a second physical feature different from the first physical feature, to generate second parameters (fig 5-7 and related text, the loop/iteration process in fig 5-7 repeat the simulation/ validation/ evaluation to generate second/third/subsequent/new/optimized parameters/values);
comparing (by fig 5-7 and related text) the first and the second parameters with preset parameters; and
when the first and the second parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data (When the process in fig 5-7 satisfy/meet / comply with the preset/predefined parameters/ values/ range/limits/specification, the IC is manufactured based on the layout created).
(Claims 2) when the first and the second parameters do not meet the preset parameters, adjusting the first specification data to generate second specification data; and after the first specification data is adjusted, generating the first and the second parameters based on the second specification data (see fig 5-7 and related text)
(Claim 3) selecting the first evaluation operation and second first evaluation operation from a plurality of evaluation operations according to the first specification data (see fig 5-7 and related text, i.e., evaluations/ simulations/ validations / verification met/complied/satisfied are selected).
(Claim 4) when the first specification data includes data corresponding to a third physical feature, selecting a third evaluation operation corresponding to the third physical feature from the plurality of evaluation operations; when the third evaluation operation is selected, performing the third evaluation operation to the first specification data, to generate third parameters; comparing the first parameters, the second parameters and the third parameters with the preset parameters; and when the first parameters, the second parameters and the third parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data ((see fig 5-7 and related text, i.e., the loop/iteration process of evaluations/ simulations/ validations / verification produce various parameters/values until the design/specification are meet/complied/satisfied).
(Claim 5) wherein when the first specification data does not include the data associated with the third physical feature, the third evaluation operation is not performed.
(Claim 6) extracting (the loop/iteration process in fig 5-7 feedback/extract/derive data/values/parameters/data) physical data from the first specification data; dividing the semiconductor device into a plurality of grids (fig 1-7); generating grid data (fig 1-7) according to the physical data; and generating the first parameters according to the grid data (fig 1-7), wherein the grid data includes physical values of each of the plurality of grids (fig 1-7).
(Claim 7) extracting (the loop/iteration process in fig 5-7 feedback/extract/derive data/values/parameters/data) first physical data and second physical data from the first specification data; comparing (fig 5-7) the first physical data with preset element parameters; when the first physical data do not meet the preset element parameters, adjusting the first specification data (fig 5-7); and when the first physical data meets the preset element parameters, generating the first parameters according to the first physical data and the second physical data, wherein the first physical data is different from the second physical data (fig 5-7).
Claims 9-12, 14-15 and 17-18 recite similar subject matter and are rejected for the same reason.
Allowable Subject Matter
Claims 8, 13, 16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8, 13, 16 and 19-20 would be allowable because the prior art of record does not teach or suggest the limitations in these claims.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851
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