DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schenck, US Patent 4,238,757
Regarding claim 7, Schenck teaches a device comprising: a liquid gated transistor 24/22/12/13/11; a circuit (column 1, line 68 to column 2, line 10,wherein the voltage being applied is by a circuit); and first and second electrodes (17, 18), each of which is coupled to a respective one of the liquid gated transistor and the circuit, wherein the circuit is configured to apply a voltage across the first and second electrodes (column 1, line 68 to column 2, line 10 and figure 1,wherein the voltage being applied is by a circuit).
Regarding claim 8, Schenck teaches an insulator 20 between the liquid gated transistor and the circuit (figure 1).
Regarding claim 9, Schenck teaches the insulator defines a recess aligned with a pore in the liquid gated transistor (wherein gate electrode 23 sits in in figure 1)
Regarding claim 10, Schenck teaches an interconnection that interconnects the liquid gated transistor, the electrodes, and the circuit (as shown in figure below).
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Regarding claim 11, Schenck teaches circuit defines a recess therethrough aligned with a pore in the liquid gated transistor (as shown above).
Regarding claim 12, Schenck teaches a wafer 20 between the circuit (which is on the end of 24) and the second electrode 17 and 18 (figure 1)
.
Regarding claim 13, Schenck teaches the wafer defines a recess therethrough aligned with a pore in the liquid gated transistor.
Regarding claim 14, Schenck teaches third 23 and fourth 24 electrodes coupled to the liquid gated transistor, wherein the circuit is further configured to apply a second voltage across the third and fourth electrodes (figure 1).
Regarding claim 15, Schenk teaches a system comprising: a liquid gated transistor 24/22/12/13/11 (column 2, lines 58-59); a pair of electrodes 17, 18 coupled to the liquid gated transistor; and a circuit configured to apply a voltage across the electrodes (column 1, line 68 to column 2, line 10 and figure 1,wherein the voltage being applied is by a circuit).
Regarding claim 16, Schenck teaches a chamber 10, wherein the liquid gated transistor is mounted on the chamber (figure 1).
Regarding claim 17, Schenck teaches an insulator 20 between the liquid gated transistor and the circuit (figure 1).
Regarding claim 18, Schenck teaches the insulator defines a recess therethrough aligned with a pore in the liquid gated transistor (wherein gate electrode 23 sits in in figure 1)
Regarding claim 19, Schenck teaches an interconnection that interconnects the liquid gated transistor, the electrodes, and the circuit (as shown in figure above).
Regarding claim 20, Schenck teaches the circuit defines a recess therethrough aligned with a pore in the liquid gated transistor (wherein the pore contains electrode 24 in figure 1).
Allowable Subject Matter
Claims 1-6 are allowed. The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art fails to anticipate or render obvious the claimed invention including “...driving, by a circuit, a biomolecule through a pore in a liquid gated transistor; and outputting, by the circuit, a parameter associated with the biomolecule...” Claims 2-7 are dependent upon claim 1 and are therefore allowable.
With regards to claim 1, the closest art that meets this limitation is Mandell (et al, US Patent Application Publication 2023/0090867). However, this art does not qualifies as prior art. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 1-7 have been found to be allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899