DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of (Group I), claims 1-12 in the reply filed on 3/11/2026 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claims (Group II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/11/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (20210098399) in view of Su (20210335792)
Regarding Claim 1, in Fig. 20, Wu discloses a semiconductor device, comprising: a substrate 101; a first dielectric layer 103, disposed on the substrate; a conductive layer 125a/125b/125c/125d, disposed on the first dielectric layer, wherein the conductive layer comprises a plurality of conductive wires (see paragraphs 0079-0084 and 0092, bit lines); an insulating capping layer 127 (paragraphs 0092, 0093 0094, 0096), disposed on the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers (see paragraphs 0092, 0094). Although, in paragraphs 0058 and 0059 Wu mentions about a (buried) gate, it expressly fails to disclose a gate structure, disposed on a top surface of the substrate; a first conductive element, being in contact with a first conductive wire among the conductive wires; and a second conductive element, being in contact with a second conductive wire among the conductive wires. However, in Figs. 26-30, Wu discloses
a gate structure 125A, disposed on a top surface of the substrate 101; a first conductive element 105 being in contact with a first conductive wire 133A/135A (bit lines) among the conductive wires (bit lines, see paragraphs 0066, 0076); and a second conductive element 105 being in contact with a second conductive wire 133A/135A (bit lines) among the conductive wires (bit lines, see paragraphs 0066, 00076) (Please note that bit lines have air gaps spacers 145). Wu fails to disclose the required gate structure disposed on the top surface of the substate. However, Su discloses a semiconductor device where the gate structure 125 on top surface of the substrate 101 is disclosed
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required gate structure in Wu as taught by Su in order to be able to use the device of Wu in memory applications.
Regarding Claim 2, in Fig. 20 of Wu, a first insulating layer, 145 disposed on the conductive wires.
Regarding Claim 3, in Fig. 20 of Wu, a second dielectric layer 129, disposed on the first insulating layer.
Regarding Claim 4, in Fig. 20 of Wu, a second insulating layer 131, disposed on the second dielectric layer 129, and filling a plurality of second gaps of the second dielectric layer 129 along lateral directions.
Regarding Claim 5, in Fig. 20 of Wu, the second insulating layer 131, the first insulating layer 145, and the second dielectric layer 129 above a first top surface of the conductive layer 129 are polished, so that a remaining first insulating layer 145 and a remaining second dielectric layer 129 are exposed.
Regarding Claim 6, in Fig. 20 of Wu, in paragraph 0070, the second dielectric layer comprises silicon oxide.
Regarding Claim 7, in Fig. 20 of Wu, the insulating capping layer 127, the first insulating layer 145, and the second insulating layer 131 are made of a first insulating material.
Regarding Claim 8, in Fig. 20 of Wu, the first insulating material comprises silicon nitride (see paragraph 0093).
Regarding Claim 9, in Fig. 20 of Wu, each air 161 spacer is surrounded by the insulating capping layer 127, the remaining first insulating layer 145, the remaining second dielectric layer 129, and the remaining second insulating layer 131.
Regarding Claim 10, in Figs. 26-30 of Su, a first spacer 145, disposed between the first conductive element 105 and the gate structure 125A; and a second spacer 141, disposed between the second conductive element 105 and the gate structure 125A.
Regarding Claim 11, in Figs. 26-30 of Su, the first spacer 145 and the second spacer are 141 made of an insulating material, (i.e. air for spacer 145 and silicon nitride or spacer 141).
Regarding Claim 12, in Figs. 26-30 of Su, the gate structure 125A comprises: a gate oxide 117, disposed on the top surface of the substrate 101; and a gate terminal 119A/121A/123, disposed on the gate oxide.
CITED ART THAT IS NOT RELIED UPON
Examiner is including Huang (20220254898) as pertinent art that is NOT relied upon but that do disclose airgap structures in order to prevent interference/overlap capacitance between the conductive bit-lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAZLI ERDEM/Primary Examiner, Art Unit 2812 3/21/2026
Prosecution Insights