DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II in the reply filed on 31 March 2026 is acknowledged. The traversal is on the ground(s) that dependent claims 17 and 20 contain limitations presented in claim 1. This is not found persuasive because claim 1 recites the limitations of “further operations to provide nonvolatile memory cells on the monolithic integrated circuit substrate with no additional thermal budget, with no additional implant operations, and with only a single additional mask, relative to the sequence of process operations”, which is mutually exclusive to Group II claims and requires a different search.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al, US Patent 9,349,654 in view of Yamamoto et al, US Patent 6,359,318 and Chen et al, US Patent Application Publication 2014/0319622
Regarding claim 10, Li teaches an integrated circuit manufacturing method that comprises:
forming one or more isolation structures 130 to isolate between multiple regions of a semiconductor substrate, the multiple regions including at least one MOS device region (regions two or three, abstract), and at least one nonvolatile memory region (region one, abstract, column 2, lines 11-12);
forming a pad oxide layer 172/176 over the multiple regions (figure 1b);
performing ion-implantation of impurities through the pad oxide layer to form at least one well or buried layer in each of the multiple regions (column 3, lines 23-25 and 34-36 and figure 1b);
depositing an additional layer 148 over the pad oxide layer;
heating to anneal away damage from the ion-implantation concurrently with densifying the oxide-additional layer (column 3, lines 60-67); and
using a mask 180 to define one or more portions of the oxide-additional layer stack to each serve as a state element in the at least one nonvolatile memory region (figure 1d).
Li fails to teach the multiple regions including at least one bipolar device region, the additional layer is made of a silicon nitride layer, and depositing a sandwich oxide layer over the silicon nitride layer to form an oxide- nitride-oxide stack.
However, Li does teach a substrate that contains different regions (see abstract and column 2, lines 10-18). Yamamoto teaches that a bipolar device (npn bipolar transistor device, figure 1) is a generally-known type of device that is used in making electrical components.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yamamoto with that of Li because a bipolar device is a generally-known type of device that is used in making electrical components.
Li and Yamamoto fail to teach the additional layer is made of a silicon nitride layer and depositing a sandwich oxide layer over the silicon nitride layer to form an oxide- nitride-oxide stack.
However, figure 7 of Chen teaches that the additional layer structure formed on the pad oxide layer 106 may include a bi-layer of 108 (nitride, [0040]) and 140 (sandwich oxide layer) and additional layer 108 is made of a silicon nitride layer and depositing a sandwich oxide layer 140 over the silicon nitride layer to form an oxide- nitride-oxide stack (figure 7, [0040-0041]). Oxide-nitride-oxide layer stacks are generally-used in the art as a means to better protect the underlying semiconductor substrate better than a single or dual layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen with that of Li and Yamamoto because oxide-nitride-oxide layer stacks are generally-used in the art as a means to better protect the underlying semiconductor substrate better than a single or dual layer.
Regarding claim 11, Li in view of Chen teaches removing the oxide-nitride-oxide stack except for the one or more state elements (taught in figure 1e of Li using the oxide-nitride-oxide structure taught in Chen, in which the ono stack is removed in region 122).
Regarding claim 12, Li teaches removing includes performing a reactive ion etch to remove the sandwich oxide layer (by teaching the removal of an oxide layer by RIE (column 2, line 55-58, and column 2, line 66 to column 3, line 2).
Regarding claim 13, Li teaches said removing further includes performing a second reactive ion etch to remove the silicon nitride layer (by teaching the removal of an nitride layer by RIE (column 2, line 55-58, and column 2, line 66 to column 3, line 2).
Regarding claim 14, Li teaches said removing further includes performing a wet etch to remove the pad oxide layer (by removing an oxide, in column 4,line 28-30)
Regarding claim 15, Li teaches removing the mask (figure 1e-1h); providing a gate dielectric layer 150, 152, 170 and forming a gate 165, 163, 169 over each of the one or more state elements and a gate 165, 163, 169 over the gate dielectric layer at each location of one or more MOS devices (figure 1o).
Regarding claim 16, Yamamoto teaches using the gates to form self-aligned sources 21 and drains 21 for the one or more state elements (CMOS) and the one or more MOS devices (12 and 13 in npn bipolar transistor region in figure 1).
Regarding claim 17, Yamamoto teaches creating gate contacts 53 to the gates and surface contacts to the sources and drains and to wells in the at least one bipolar device region, at least some of the gate contacts and surface contacts forming terminals for 2T SONOS memory cells in the at least one nonvolatile memory region, terminals for MOS devices in the at least one MOS device region, and terminals for bipolar devices in the at least one bipolar device region (figure 1)
Regarding claim 18, Li teaches an integrated circuit manufacturing method that comprises:
forming one or more isolation structures 130 configured to isolate between multiple regions of a semiconductor substrate, the multiple regions including at least one MOS device region (regions two or three, abstract), and at least one nonvolatile memory region (column 3, lines 23-25 and 34-36 and figure 1b);
performing ion implantation to form one or more wells in each of the at least one MOS device region and other device regions (column 3, lines 25-27);
forming an oxide-additional layer stack 172/176/184 in the at least one nonvolatile memory region before annealing away damage from the ion implantation, the annealing serving to densify the oxide-additional layer stack (column 3, lines 60-67);
using a mask 180 to protect one or more portions of the oxide-additional layer stack while removing a remainder portion of the oxide-additional layer stack (figure 1d);
forming a gate dielectric layer 152, 150, 170 in place of said remainder portion (figure 1f, 1h, 1m); and
patterning a gate electrode 165, 163, 169 over each of the one or more portions while also patterning a gate electrode at each of one or more MOS device gate locations in each of the at least one MOS device region and the at least one nonvolatile memory region (figure 1o)
Li fails to teach the multiple region including at least one bipolar device region and the additional layer includes a nitride-oxide.
However, Li does teach a substrate that contains different regions (see abstract and column 2, lines 10-18). Yamamoto teaches that a bipolar device (npn bipolar transistor device, figure 1) is a generally-known type of device that is used in making electrical components.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yamamoto with that of Li because a bipolar device is a generally-known type of device that is used in making electrical components.
Li and Yamamoto fail to teach the additional layer includes a nitride-oxide.
However, figure 7 of Chen teaches that the additional layer structure formed on the pad oxide layer 106 may include a bi-layer of 108 (nitride, [0040]) and 140 (sandwich oxide layer) and additional layer 108 is made of a silicon nitride layer and depositing a sandwich oxide layer 140 over the silicon nitride layer to form an oxide- nitride-oxide stack (figure 7, [0040-0041]). Oxide-nitride-oxide layer stacks are generally-used in the art as a means to better protect the underlying semiconductor substrate better than a single or dual layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen with that of Li and Yamamoto because oxide-nitride-oxide layer stacks are generally-used in the art as a means to better protect the underlying semiconductor substrate better than a single or dual layer.
Regarding claim 19, Yamamoto teaches using the gate electrodes to form self-aligned sources and drains (12, 13, 21 in figure 1).
Regarding claim 20, Yamamoto teaches creating gate contacts 53 to the gate electrodes and surface contacts to the sources and drains and to the one or more wells, the gate contacts and surface contacts providing terminals for 2T SONOS cells in the at least one nonvolatile memory region, terminals for MOS devices in the at least one MOS device region, and terminals for bipolar devices in the at least one bipolar device region (figure 1)
Conclusion
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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