DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group I, claims 1-11 and new claims 21-29, the reply filed on 4/1/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant’s cancellation of non-elected claims 12-20 is acknowledged.
Allowable Subject Matter
Claims 23 and 29 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lin[1] et al., US Publication No. 2022/0359720.
Lin[1] anticipates:
1. A method comprising (see figs. 5B-5D, also see figs. 1-15):
forming a protruding fin (26);
forming a first dielectric layer (38) comprising:
a first top portion (T1-T) on a top surface of the protruding fin; and
a first sidewall portion (T1-B) on a sidewall of the protruding fin;
forming a second dielectric layer (40) over the first top portion of the first dielectric layer and the top surface of the protruding fin (26), wherein the second dielectric layer is formed using an anisotropic deposition process (e.g. see para. [0026], fig. 17);
forming a dummy gate electrode (42) on the second dielectric layer;
forming a gate spacer (46) on a sidewall of the dummy gate electrode;
removing the dummy gate electrode; and
forming a replacement gate electrode (64) in a space left by the dummy gate electrode. See Lin at para. [0001] – [0072], figs. 1-19.
2. The method of claim 1, wherein the second dielectric layer (40) is free from portions on the first sidewall portion of the first dielectric layer, para. [0023], fig. 5C.
3. The method of claim 1, wherein the first dielectric layer (e.g. CVD, para. [0021]) and the second dielectric layer (e.g. plasma ALD, para. [0026]) are formed using different deposition methods.
4. The method of claim 3, wherein the first dielectric layer is deposited using a conformal deposition method, para. [0021].
5. The method of claim 1, wherein the second dielectric layer is deposited using plasma enhanced atomic layer deposition, with a bias power applied, para. [0026] – [0028], fig. 17.
6. The method of claim 1 further comprising, after the dummy gate electrode is removed and before the replacement gate electrode is formed, etching exposed portions of the first dielectric layer and the second dielectric layer, para. [0057], fig. 9.
7. The method of claim 6, wherein after the exposed portions of the first dielectric layer and the second dielectric layer are etched, a first part of the first dielectric layer and a second part of the second dielectric layer remain directly underlying the gate spacer, para. [0057], fig. 9.
8. The method of claim 7, wherein the second part of the second dielectric layer (40) directly underlying the gate spacer (46) is non-conformal, figs. 5C-5D and fig. 9.
10. The method of claim 1, wherein the forming the dummy gate electrode comprises depositing a polysilicon layer on the second dielectric layer, and patterning the polysilicon layer, wherein the patterning is stopped on the second dielectric layer, para. [0054].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin[1], as applied to claim 1 above, in view of Cheng et al., US Publication No. 20200266060 A1.
Regarding claim 9:
Lin[1] teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the protruding fin comprises a plurality of semiconductor nanostructures stacked and spaced apart from each other, and wherein the replacement gate electrode extends into spaces between the plurality of semiconductor nanostructures.
In an analogous art, Cheng teaches gate-all-around FET devices include vertical fin-type FETs, nanowire FETs, and other types of GAA FET devices having gate structures that are formed around all sides of active channel layers, para. [0031].
Cheng teaches that a vertical fin-type FETs and nanowire FETs (-i.e. nanostructure FETs) are considered equivalent gate-all-around FETs known in the art. Therefore, because these two transistors were art-recognized equivalents, one of ordinary skill in the art would have found it obvious to substitute Lin[1]’s vertical fin for a “protruding fin comprising a plurality of semiconductor nanostructures stacked and spaced apart from each other”, as recited in the claim. Also see MPEP § 2144.06, Art Recognized Equivalence for the Same Purpose.
Cheng further teaches:
(see figs. 11-12) wherein the replacement gate electrode (174) extends into spaces between the plurality of semiconductor nanostructures (112, 114, 116), para. [0072] – [0082].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lin[1] with the teachings of Cheng because “In addition, with nanowire/nanosheet FET devices, a common gate structure is formed above and below each nanowire/nanosheet layer in the stacked configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area.” See Cheng at para. [0002].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin[1], as applied to claim 1 above.
Regarding claim 11:
Lin[1] teaches all the limitations of claim 1 above, and further teaches:
11. The method of claim 10, wherein the second dielectric layer (40) comprises a second sidewall portion on the first sidewall portion, figs. 5B and 5D.
Lin[1] is silent regarding a cleaning process.
However, it would have been obvious to one of ordinary skill in the art to perform “wherein the second sidewall portion is removed in a cleaning process performed before the forming the gate spacer” because Lin[1], at para. [0055], teaches the second dielectric layer (40) is “etched” (-i.e. “removed” as recited in the claim) .
Claim(s) 21, 22, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin[2], et al., US Publication No. 2022/0384611 A1 in view of Cheng et al., US Publication No. 20200266060 A1.
Lin[2] teaches:
21. A method comprising (see figs. 1-24):
forming a plurality of semiconductor nanostructures (e.g. fin 60 formed as nanostructures per para. [0012]) aside of, and higher than, a dielectric isolation region (70), wherein higher ones of the plurality of semiconductor nanostructures overlap respective lower ones of the plurality of semiconductor nanostructures;
(see fig. 7) depositing a first dielectric layer (e.g. 80A, para. [0030]) on a top surface and a sidewall of the plurality of semiconductor nanostructures, wherein the first dielectric layer is deposited in a first deposition process;
(see fig. 8) depositing a second dielectric layer (e.g. 80B, para. [0032]) comprising a first part over the first dielectric layer (80A), wherein the second dielectric layer is deposited in a second deposition process (e.g. PEALD, para. [0032]) that is less conformal than the first deposition process (e.g. CVD, para. [0030]), and wherein at least a top portion of the first part is higher than the top nanostructure of the plurality of semiconductor nanostructures (e.g. fin 60 formed as nanostructures per para. [0012]);
forming a gate stack (80, see Remarks below) comprising:
a first portion over a top nanostructure of the plurality of semiconductor nanostructures (e.g. fin 60 formed as nanostructures per para. [0012]); and
second portions between neighboring ones of the plurality of semiconductor nanostructures, wherein the second portions of the gate stack and the plurality of semiconductor nanostructures connectively form a protruding fin (e.g. fin 60 formed as nanostructures per para. [0012]);
and
forming a gate spacer (6) over the second dielectric layer (80B). See Lin[2] at para. [0001] – [0071].
Regarding claim 21:
In the embodiment shown in figs. 1-24, Lin[2] shows a channel comprising a fin rather than a plurality of semiconductor nanostructures. However, it would have been obvious to one of ordinary skill in the art to modify figs. 1-24 to form the channel to comprise a plurality of semiconductor nanostructures because Lin[2] discloses the teachings can be applied to semiconductor nanostructures at para. [0012]:
“Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like.”
Furthermore, in an analogous art, Cheng teaches gate-all-around FET devices include vertical fin-type FETs, nanowire FETs, and other types of GAA FET devices having gate structures that are formed around all sides of active channel layers, para. [0031].
Cheng teaches:
(see fig. 1) forming a gate stack (174) comprising:
a first portion over a top nanostructure (116) of the plurality of semiconductor nanostructures (112, 114, 116); and
second portions between neighboring ones of the plurality of semiconductor nanostructures (114, 116), wherein the second portions of the gate stack and the plurality of semiconductor nanostructures connectively form a protruding fin, para. [0035] – [0041].
Further regarding claim 21:
MPEP § 2111.01, “Plain Meaning” indicates:
Although the specification discussed only a single embodiment, the court held that it was improper to read a specific order of steps into method claims where, as a matter of logic or grammar, the language of the method claims did not impose a specific order on the performance of the method steps, and the specification did not directly or implicitly require a particular order.
22. The method of claim 21, wherein the first deposition process is a conformal deposition process (e.g. CVD, para. [0030]), and the first part of the second dielectric layer (80B) has a bottommost end substantially level with a topmost surface of the top nanostructure (e.g. fin 60 formed as nanostructures per para. [0012]), fig. 8
24. The method of claim 21, wherein the first portion of the second dielectric layer (80B) further comprises a second part on a sidewall of the protruding fin, and wherein the second part is thinner than the first part, para. [0032].
25. The method of claim 24, wherein a bottommost end of the second part is higher than a mid-height of the protruding fin, para. [0032], fig. 8.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lin[2] with the teachings of Cheng because “In addition, with nanowire/nanosheet FET devices, a common gate structure is formed above and below each nanowire/nanosheet layer in the stacked configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area.” See Cheng at para. [0002].
Claim(s) 26, 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al., US Publication No. 2019/0385916 A1 in view of Lin[2], et al., US Publication No. 2022/0384611 A1.
Song teaches:
26. A method comprising (see figs. 1-9):
forming a first dielectric isolation region (120) and a second dielectric isolation region (120) in a semiconductor substrate (110);
forming a protruding fin (115) between, and higher than, the first dielectric isolation region and the second dielectric isolation region;
depositing a first dielectric layer (130) on a top surface and a sidewall of the protruding fin;
depositing a second dielectric layer (160) over the first dielectric layer, the second dielectric layer comprising:
(see fig. 3) a first portion (160) overlapping the protruding fin (115); and
(see fig. 3) a second portion (160) overlapping the first dielectric isolation region (120), wherein the first portion and the second portion are discrete portions of the second dielectric layer; and… See Song at para. [0001] – [0074].
Regarding claim 26:
Song does not expressly teach:
forming a gate spacer over the second dielectric layer.
However, Song teaches after fig. 9, processes are conducted to form gate structures at para. [0067] – [0071].
In an analogous art, Lin[2] teaches to form gate structures a gate spacer (100) is formed so that source/drain regions are separated by an appropriate lateral distance to prevent short out. See Lin[2] at para. [0050].
It would have been obvious to a person of ordinary skill in the art to modify Song with Lin[2] to form “gate spacer over the second dielectric layer” so that source/drain regions are separated by an appropriate lateral distance to prevent short out.
27. The method of claim 26, wherein the gate spacer physically contacts a sidewall part of the first dielectric layer, and wherein the gate spacer is spaced apart from a top part of the first dielectric layer by the first portion of the second dielectric layer.
28. The method of claim 26, wherein the first dielectric layer (130) comprises silicon oxide, and the second dielectric layer (160) comprises silicon and an element selected from the group consisting of N, C, and combinations thereof, para. [0041], [0055].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Song with the teachings of Lin[2] because a gate spacer enables source/drain regions to be separated by an appropriate lateral distance to prevent short out. See Lin[2] at para. [0050].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
3 June 2026
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