Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘Figs. 4A-4F’ in the paragraph [0006] are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-13 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pidin (US 20210210601).
Regarding claim 1. Fig 57 of Pidin discloses A semiconductor structure, comprising:
first 458 (the second 458 from the topmost 458) and second 458 (the bottommost 458) channel structures [0161] on a substrate 401;
a gate structure 455/457/1044 [0241] on the first and second channel structures;
an epitaxial structure 1031p/1015p [0254] on the first and second channel structures ([0220]: ‘p-type semiconductor layers are epitaxially grown’),
wherein the epitaxial structure is at a first side (right side) of the gate structure;
a first source/drain (S/D) contact structure 1408 on the first channel structure (contacting on 1032p), wherein the first S/D contact structure is at a second side (left side) of the gate structure opposite to the first side; and
a second S/D contact structure 1306 on the second channel structure (contacting on 1016p), wherein the second S/D contact structure is at the second side of the gate structure (Fig 57).
Regarding claim 2. Pidin discloses The semiconductor structure of claim 1, wherein the first S/D contact structure is separated from the second S/D contact structure (Fig 57).
Regarding claim 3. Pidin discloses The semiconductor structure of claim 1, further comprising a third S/D contact structure 1407 on the epitaxial structure (Fig 57).
Regarding claim 4. Pidin discloses The semiconductor structure of claim 1, further comprising a gate contact structure 1071 on the gate structure (Fig 57).
Regarding claim 5. Pidin discloses The semiconductor structure of claim 4, wherein the gate contact structure extends over the first and second channel structures (Fig 57).
Regarding claim 7. Pidin discloses The semiconductor structure of claim 1, further comprising a third channel structure 458 (the third 458 from the topmost 458) on the substrate, wherein:
the epitaxial structure is on the third channel structure (Fig 57: refer to 1015p);
the gate structure is on the third channel structure (Fig 57); and
a first distance between the second and third channel structures is equal to a second distance between the first and second channel structures (Fig 57).
Regarding claim 8. Pidin discloses The semiconductor structure of claim 1, further comprising third 458 (the topmost 458) and fourth 458 (the third 458 from the topmost 458) channel structures on the substrate, wherein:
the epitaxial structure is on the third and fourth channel structures (Fig 57);
the gate structure is on the third and fourth channel structures (Fig 57); and
a first distance between the second and third channel structures is greater than a second distance between the first and second channel structures (Fig 57).
Regarding claim 11. Fig 57 of Pidin discloses A semiconductor device, comprising:
a first transistor (the transistor above 432) on a substrate, wherein the first transistor comprises:
a first channel structure 458 (above 432) on the substrate;
a gate structure 455/457/1044 on the first channel structure;
an epitaxial structure 1031p/1015p on the first channel structure at a first side (right side: refer to the 1031p of the 1031p/1015p) of the gate structure; and
a first source/drain (S/D) contact structure 1408 on the first channel structure at a second side (left side) of the gate structure opposite to the first side; and
a second transistor (the transistor below 432) on the substrate, wherein the second transistor comprises:
a second channel structure 458 (below 432) on the substrate;
the gate structure on the second channel structure (Fig 57);
the epitaxial structure on the second channel structure at the first side of the gate structure (refer to the 1015p of the 1031p/1015p); and
a second S/D contact structure 1306 on the second channel structure at the second side of the gate structure, wherein the second S/D contact structure is separate from the first S/D contact structure (Fig 57).
Regarding claim 12. Pidin discloses The semiconductor device of claim 11, further comprising a third S/D contact structure 1407 on the epitaxial structure, wherein the third S/D contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 13. Pidin discloses The semiconductor device of claim 11, further comprising a gate contact structure 1071 on the gate structure, wherein the gate contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 17. Fig 6B (intermediate processing step) and Fig 57 ([0115]: final device from Fig 6B) of Pidin disclose A method, comprising:
forming first 458 (the 458 above 432) and second 458 (the 458 below 432) channel structures on a substrate 401;
forming a gate structure 455/457/1044 on the first and second channel structures;
forming, at a first side (right side) of the gate structure, an epitaxial structure 1031p/1015p on the first and second channel structures; and
forming, at a second side (left side) of the gate structure opposite to the first side, a first source/drain (S/D) contact structure 1408 on the first channel structure and a second S/D contact structure 1306 on the second channel structure, wherein the first and second S/D contact structures are separated from each other (Fig 57).
Regarding claim 18. Pidin discloses The method of claim 17, further comprising forming a third S/D contact structure 1407 on the epitaxial structure, wherein the third S/D contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 19. Pidin discloses The method of claim 17, further comprising forming a gate contact structure 1071 on the gate structure, wherein the gate contact structure extends over one or more of the first and second channel structures (Fig 57).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Pidin (US 20210210601).
Regarding claim 6. Pidin discloses The semiconductor structure of claim 1. But Pidin does not explicitly disclose wherein a ratio of a thickness of the epitaxial structure to a height of the first and second channel structures ranges from about 0.25 to about 0.5.
However, the ordinary artisan would have recognized the claimed ratio range to be a result effective variable affecting device performance and short-channel effects. This ratio impacts the contact resistance, carrier injection into the channel, and overall device electrostatics. Thus, it would have been obvious that the ratio of the Pidin’s device within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed ratio range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 14. Pidin discloses The semiconductor device of claim 11. But Pidin does not explicitly disclose wherein a ratio of a thickness of the epitaxial structure to a height of the first channel structure ranges from about 0.25 to about 0.5.
However, the ordinary artisan would have recognized the claimed ratio range to be a result effective variable affecting device performance and short-channel effects. This ratio impacts the contact resistance, carrier injection into the channel, and overall device electrostatics. Thus, it would have been obvious that the ratio of the Pidin’s device within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed ratio range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pidin (US 20210210601) in view of Chang (US 20200176328).
Regarding claim 20. Pidin discloses The method of claim 17 except further comprising: doping the first and second channel structures with a dopant; and diffusing the dopant along the first and second channel structures.
However, Chang discloses doping the first and second channel structures with a dopant; and diffusing the dopant along the first and second channel structures [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Chang doping process within the Pidin’s method for the purpose of providing enhanced controllability over carrier concentration, creating tailored electric fields for better transistor performance, and enhanced mobility, crucial for designing efficient Field-Effect Transistors (FETs) and integrated circuits by balancing conductivity and short-channel effects.
Allowable Subject Matter
Claims 9-10 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first channel structure has a first width; the second channel structure has a second width less than the first width; the first and second channel structures comprise a dopant; and a first concentration of the dopant in the first channel structure is less than a second concentration of the dopant in the second channel structure”.
Regarding claim 10. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “an additional gate structure at the first side of the gate structure, the epitaxial structure is between the gate structure and the additional gate structure; a third S/D contact structure on the first channel structure; and a fourth S/D contact structure on the second channel structure, the third S/D contact structure is separated from the fourth S/D contact structure, and the third and fourth S/D contact structures and the epitaxial structure are at opposite sides of the additional gate structure”.
Regarding claim 15. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first, second, and additional transistors include a first number of groups of channel structures; each group includes a second number of channel structures; and a first distance between each group is greater than a second distance between the channel structures in each group”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812