Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 4/21/26 has been entered.
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the fee set forth in 37 CFR 1.17(p) on 3/12/26 prompted the new ground(s) of rejection presented in this Office action.
Furthermore, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-14 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Pidin (US 20210210601) in view of Doornbos (US 20200043921; provided in the IDS on 3/12/26).
Regarding claim 1, Fig. 57 of Pidin discloses a semiconductor structure comprising:
first 458 (the second 458 from the topmost 458) and second 458 (the bottommost 458) channel structures [0161] on a substrate 401;
a gate structure 455/457/1044 [0241] on the first and second channel structures;
an epitaxial structure 1031p/1015p [0254] on the first and second channel structures ([0220]: ‘p-type semiconductor layers are epitaxially grown’),
wherein the epitaxial structure is at a first side (right side) of the gate structure;
a first source/drain (S/D) contact structure 1408 on the first channel structure (contacting on 1032p), wherein the first S/D contact structure is at a second side (left side) of the gate structure opposite to the first side; and
a second S/D contact structure 1306 on the second channel structure (contacting on 1016p), wherein the second S/D contact structure is at the second side of the gate structure (Fig 57).
But Pidin does not explicitly disclose the epitaxial structures being on top surfaces of the first and second channel structures.
Doornbos discloses epitaxial structures 50A/50B on top surfaces of channel structures 20A/20B, respectively, as shown in Figs. 21A and 21D and described in [0071]. In particular, Fig. 21D illustrates epitaxial structures 50A/50B enclosing top surfaces of channel structures 20A/20B.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the epitaxial structures of Pidin on top surfaces of the channel structures as taught by Doornbos in order to improve epitaxial source/drain integration, electrical connection, and semiconductor device formation in transistor structures.
Regarding claim 2, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. Pidin further discloses the first S/D contact structure is separated from the second S/D contact structure (Fig 57).
Regarding claim 3, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. Pidin further discloses further comprising a third S/D contact structure 1407 on the epitaxial structure (Fig 57).
Regarding claim 4, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. Pidin further discloses comprising a gate contact structure 1071 on the gate structure (Fig 57).
Regarding claim 5, Pidin in view of Doornbos discloses the semiconductor structure of claim 4. Pidin further discloses the gate contact structure extends over the first and second channel structures (Fig 57).
Regarding claim 6, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. But Pidin in view of Doornbos explicitly discloses wherein a ratio of a thickness of the epitaxial structure to a height of the first and second channel structures ranges from about 0.25 to about 0.5.
However, the relative dimensional relationship between epitaxial structure thickness and channel height is a result-effective variable affecting semiconductor device operation. In particular, the thickness of the epitaxial structure relative to the channel height impacts source/drain resistance, contact resistance, carrier injection efficiency, parasitic resistance, electrostatic control, and short-channel effects. One of ordinary skill in the art would have recognized that modifying the relative dimensions of the epitaxial structures and channel structures predictably affects device performance characteristics and manufacturability.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of epitaxial structure thickness to channel height through routine experimentation to obtain suitable device performance characteristics, including a ratio within the claimed range of about 0.25 to about 0.5. Discovering an optimum or workable value of a result-effective variable involves only routine skill in the art. See MPEP § 2144.05(II)(B); In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980).
It is further noted that the specification does not identify the claimed ratio range of about 0.25 to about 0.5 as critical, nor does the specification attribute any particular technical significance or unexpected results to the claimed range relative to other ratio values. Absent a showing of criticality or unexpected results associated with the claimed numerical range, optimizing a result-effective variable through routine experimentation would have been within the level of ordinary skill in the art. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 7, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. Pidin further discloses a third channel structure 458 (the third 458 from the topmost 458) on the substrate, wherein:
the epitaxial structure is on the third channel structure (Fig 57: refer to 1015p);
the gate structure is on the third channel structure (Fig 57); and
a first distance between the second and third channel structures is equal to a second distance between the first and second channel structures (Fig 57).
Regarding claim 8, Pidin in view of Doornbos discloses the semiconductor structure of claim 1. Pidin further discloses comprising third 458 (the topmost 458) and fourth 458 (the third 458 from the topmost 458) channel structures on the substrate, wherein:
the epitaxial structure is on the third and fourth channel structures (Fig 57);
the gate structure is on the third and fourth channel structures (Fig 57); and
a first distance between the second and third channel structures is greater than a second distance between the first and second channel structures (Fig 57).
Regarding claim 11, Fig. 57 of Pidin discloses a semiconductor device comprising:
a first transistor (the transistor above 432) on a substrate, wherein the first transistor comprises:
a first channel structure 458 (above 432) on the substrate;
a gate structure 455/457/1044 on the first channel structure;
an epitaxial structure 1031p/1015p on the first channel structure at a first side (right side: refer to the 1031p of the 1031p/1015p) of the gate structure; and
a first source/drain (S/D) contact structure 1408 on the first channel structure at a second side (left side) of the gate structure opposite to the first side; and
a second transistor (the transistor below 432) on the substrate, wherein the second transistor comprises:
a second channel structure 458 (below 432) on the substrate;
the gate structure on the second channel structure (Fig 57);
the epitaxial structure on the second channel structure at the first side of the gate structure (refer to the 1015p of the 1031p/1015p); and
a second S/D contact structure 1306 on the second channel structure at the second side of the gate structure, wherein the second S/D contact structure is separate from the first S/D contact structure (Fig 57).
But Pidin does not explicitly disclose the first S/D contact structure being on a top surface of the first channel structure.
However, Doornbos discloses epitaxial structures 50A/50B enclosing top surfaces of channel structures 20A/20B, respectively, as shown in Figs. 21A and 21D and described in [0071]. Doornbos further discloses source/drain contact structure 80C disposed over epitaxial structures 50A/50B on top surface regions of channel structures 20A/20B, as shown in Figs. 21B–21D and described in [0095].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Pidin in view of the teachings of Doornbos such that the first S/D contact structure is disposed on a top surface region of the first channel structure, because positioning source/drain contact structures over epitaxial source/drain regions on channel top surface regions improves electrical connection, source/drain contact formation, device integration, and semiconductor device scalability in transistor structures.
Regarding claim 12, Pidin in view of Doornbos discloses the semiconductor device of claim 11. Pidin further discloses comprising a third S/D contact structure 1407 on the epitaxial structure, wherein the third S/D contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 13, Pidin in view of Doornbos discloses the semiconductor device of claim 11. Pidin further discloses comprising a gate contact structure 1071 on the gate structure, wherein the gate contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 14, Pidin in view of Doornbos discloses the semiconductor device of claim 11. But Pidin in view of Doornbos explicitly discloses wherein a ratio of a thickness of the epitaxial structure to a height of the first channel structure ranges from about 0.25 to about 0.5.
However, the relative dimensional relationship between epitaxial structure thickness and channel height is a result-effective variable affecting semiconductor device operation, including source/drain resistance, contact resistance, carrier injection efficiency, parasitic resistance, electrostatic control, and short-channel effects.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of epitaxial structure thickness to channel height through routine experimentation to obtain suitable device performance characteristics, including a ratio within the claimed range of about 0.25 to about 0.5. Discovering an optimum or workable value of a result-effective variable involves only routine skill in the art. See MPEP § 2144.05(II)(B); In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980).
It is further noted that the specification does not identify the claimed ratio range of about 0.25 to about 0.5 as critical, nor does the specification attribute any particular technical significance or unexpected results to the claimed range relative to other ratio values. Absent a showing of criticality or unexpected results associated with the claimed numerical range, optimizing a result-effective variable through routine experimentation would have been within the level of ordinary skill in the art. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 17, Fig. 6B (intermediate processing stage) and Fig. 57 (final semiconductor device structure) of Pidin disclose a method comprising forming first and second channel structures 458 on substrate 401, wherein the first channel structure corresponds to the channel structure above dielectric structure 432 and the second channel structure corresponds to the channel structure below dielectric structure 432, as shown in Fig. 57.
Pidin further discloses forming gate structure 455/457/1044 on the first and second channel structures, as shown in Fig. 57 and described in [0241].
Pidin further discloses forming, at a first side of the gate structure, epitaxial structures 1031p/1015p on the first and second channel structures, as shown in Fig. 57 and described in [0220], wherein [0220] states that p-type semiconductor layers are epitaxially grown. In particular, the right side of gate structure 455/457/1044 corresponds to the claimed first side.
Pidin further discloses forming, at a second side of the gate structure opposite the first side, first source/drain (S/D) contact structure 1408 and second S/D contact structure 1306 on top surface regions of the first and second channel structures, respectively, wherein the first and second S/D contact structures are separated from each other, as shown in Fig. 57. In particular, the left side of gate structure 455/457/1044 corresponds to the claimed second side.
But Pidin does not explicitly disclose the first and second S/D contact structures being disposed on top surface regions of the channel structures through epitaxial source/drain structures.
However, Doornbos discloses epitaxial structures 50A/50B enclosing top surfaces of channel structures 20A/20B, respectively, as shown in Figs. 21A and 21D and described in [0071]. Doornbos further discloses source/drain contact structure 80C disposed over epitaxial structures 50A/50B on top surface regions of channel structures 20A/20B, as shown in Figs. 21B–21D and described in [0095].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pidin in view of the teachings of Doornbos such that the source/drain contact structures are formed on top surface regions of the channel structures through epitaxial source/drain structures, because such placement improves electrical connection, source/drain contact formation, device integration, and semiconductor device scalability in transistor structures.
Regarding claim 18, Pidin in view of Doornbos discloses the method of claim 17. Pidin further discloses comprising forming a third S/D contact structure 1407 on the epitaxial structure, wherein the third S/D contact structure extends over one or more of the first and second channel structures (Fig 57).
Regarding claim 19, Pidin in view of Doornbos discloses the method of claim 17. Pidin further discloses comprising forming a gate contact structure 1071 on the gate structure, wherein the gate contact structure extends over one or more of the first and second channel structures (Fig 57).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pidin (US 20210210601) in view of Doornbos (US 20200043921), and further in view of Chang (US 20200176328).
Regarding claim 20, Pidin in view of Doornbos teaches the method of claim 17 substantially as discussed above. But Pidin and Doornbos do not explicitly disclose doping the first and second channel structures with a dopant and diffusing the dopant along the first and second channel structures.
However, Chang discloses doping semiconductor channel structures with a dopant and diffusing the dopant along the channel structures, as described in [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the doping and dopant diffusion process of Chang into the semiconductor fabrication method of Pidin in view of Doornbos in order to provide enhanced controllability of carrier concentration, threshold voltage tuning, electric field engineering, carrier mobility optimization, and improved transistor performance in semiconductor devices. Such doping and dopant diffusion techniques are well-known process optimization techniques in field-effect transistor (FET) fabrication and integrated circuit manufacturing.
Allowable Subject Matter
Claims 9-10 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first channel structure has a first width; the second channel structure has a second width less than the first width; the first and second channel structures comprise a dopant; and a first concentration of the dopant in the first channel structure is less than a second concentration of the dopant in the second channel structure”.
Regarding claim 10. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “an additional gate structure at the first side of the gate structure, the epitaxial structure is between the gate structure and the additional gate structure; a third S/D contact structure on the first channel structure; and a fourth S/D contact structure on the second channel structure, the third S/D contact structure is separated from the fourth S/D contact structure, and the third and fourth S/D contact structures and the epitaxial structure are at opposite sides of the additional gate structure”.
Regarding claim 15. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first, second, and additional transistors include a first number of groups of channel structures; each group includes a second number of channel structures; and a first distance between each group is greater than a second distance between the channel structures in each group”.
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the fee set forth in 37 CFR 1.17(p) on 3/12/26 prompted the new ground(s) of rejection presented in this Office action.
Furthermore, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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