DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species 1a and 2a in the reply filed on April 2, 2026 is acknowledged.
Claim 8, and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 2, 2026.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "26B" and "36B" have both been used to designate the second portion of the interlayer dielectric layer in Fig. 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In ¶ [0018]: “device layer 20” should read --device layer 10--
In ¶ [0036]: “second portion 24B” should read --second portion 24C--
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (US 20220069201 A1) herein after “Yin”.
Regarding claim 1, Fig. 2A of Yin discloses a semiconductor device (Fig. 2A, semiconductor device 100A, ¶ [0027]), comprising:
a device layer (Fig. 2A, second dielectric layer 125, ¶ [0030]) comprising a first device region (Fig. 2A, logic region 101B, ¶ [0022]) and a second device region (Fig. 2A, memory region 101A, ¶ [0022]);
an interlayer dielectric layer (Fig. 2A, capping layer 160, ¶ [0033]) disposed above the device layer (125), wherein the interlayer dielectric layer (160) comprises:
a first portion (Fig. 2A, portion of 160 in surrounding 113B) disposed above the first device region (101B); and
a second portion (Fig. 2A, portion of 160 in 101A) disposed above the second device region (101A), wherein a top surface of the first portion (portion of 160 in surrounding 113B) is lower than a top surface of the second portion (portion of 160 in 101A) in a vertical direction;
a first interconnection structure (Fig. 2A, via 113B, metal line 114B, ¶ [0033]) disposed corresponding to the first device region (101B), wherein the first interconnection structure (113B, 114B) comprises first conductive lines (113B), and each of the first conductive lines (113B) is partly located in the first portion (portion of 160 in surrounding 113B) of the interlayer dielectric layer (160);
a second interconnection structure (Fig. 2A, via 113A, metal line 114A, ¶ [0033]) disposed corresponding to the second device region (101A), wherein the second interconnection structure (113A, 114A) comprises second conductive lines (113A) located in the second portion (portion of 160 in 101A) of the interlayer dielectric layer (160); and
a first dielectric layer (Fig. 2A, inter metal dielectric (IMD) layer 170, ¶ [0033]) disposed on the first portion (portion of 160 in surrounding 113B) of the interlayer dielectric layer (160), wherein a part of the first dielectric layer (170) is sandwiched between two of the first conductive lines (113B) adjacent to each other, and a bottom surface of the first dielectric layer (170) is lower than the top surface of the second portion (portion of 160 in 101A) of the interlayer dielectric layer (160) in the vertical direction.
Regarding claim 2, Fig. 2A of Yin discloses the semiconductor device according to claim 1 as applied above, and Fig. 2A of Yin further discloses wherein the bottom surface of the first dielectric layer (170) and the top surface of the first portion (portion of 160 in surrounding 113B) of the interlayer dielectric layer (160) are higher than a bottom surface of each of the first conductive lines (113B) and a bottom surface of each of the second conductive lines (113A) in the vertical direction, and
the bottom surface of the first dielectric layer (170) and the top surface of the first portion (portion of 160 in surrounding 113B) of the interlayer dielectric layer (160) are lower than a top surface of each of the first conductive lines (113B) and a top surface of each of the second conductive lines (113A) in the vertical direction.
Regarding claim 3, Fig. 2A of Yin discloses the semiconductor device according to claim 1 as applied above, and Fig. 2A of Yin further discloses wherein a top surface of each of the first conductive lines (113B) and a top surface of each of the second conductive lines (113A) are coplanar.
Regarding claim 12, Fig. 2A of Yin discloses the semiconductor device according to claim 1 as applied above, and Fig. 2A of Yin further discloses wherein the device layer (125) further comprises a third device region (Fig. 2A, passive device region 101C, ¶ [0034]), the interlayer dielectric layer (160) further comprises a third portion (portion of 160 in 101C) disposed above the third device region (101C), and a top surface of the third portion (portion of 160 in 101C) is lower than the top surface of the second portion (portion of 160 in 101A) and higher than the top surface of the first portion (portion of 160 in surrounding 113B) in the vertical direction.
Claims 1, 4-5, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (US 20220158087 A1) herein after “Kuo”.
Regarding claim 1, Fig. 10 of Kuo discloses a semiconductor device (Fig. 10, semiconductor device 100, ¶ [0036]), comprising:
a device layer (Fig. 10, “The semiconductor substrate 101 may include active components such as metal-oxide semiconductor (MOS) transistors, passive components”, ¶ [0013]) comprising a first device region (Fig. 10, memory region 16, ¶ [0036]) and a second device region (Fig. 10, logic region 14, ¶ [0036]);
an interlayer dielectric layer (Fig. 10, dielectric material layer 206, ¶ [0036]) disposed above the device layer (101), wherein the interlayer dielectric layer (206) comprises:
a first portion (Fig. 10, portion of 206 in region 16) disposed above the first device region (16); and
a second portion (Fig. 10, portion of 206 in region 14) disposed above the second device region (14), wherein a top surface of the first portion (portion of 206 in region 16) is lower than a top surface of the second portion (portion of 206 in region 14) in a vertical direction;
a first interconnection structure (Fig. 10, upper contact structure 612, ¶ [0032]) disposed corresponding to the first device region (16), wherein the first interconnection structure (612) comprises first conductive lines (Fig. 10, conductive layer 608, ¶ [0035]), and each of the first conductive lines (608) is partly located in the first portion (portion of 206 in region 16) of the interlayer dielectric layer (206);
a second interconnection structure (Fig. 10, first interconnecting structure 510, ¶ [0035]) disposed corresponding to the second device region (14), wherein the second interconnection structure (510) comprises second conductive lines (Fig. 10, conductive layer 500, ¶ [0035]) located in the second portion (portion of 206 in region 14) of the interlayer dielectric layer (206); and
a first dielectric layer (Fig. 10, etching stop layer 602, ¶ [0035]) disposed on the first portion (portion of 206 in region 16) of the interlayer dielectric layer (206), wherein a part of the first dielectric layer (602) is sandwiched between two of the first conductive lines (608) adjacent to each other, and a bottom surface of the first dielectric layer (602) is lower than the top surface of the second portion (portion of 206 in region 14) of the interlayer dielectric layer (206) in the vertical direction.
Regarding claim 4, Fig. 10 of Kuo discloses the semiconductor device according to claim 1 as applied above, and Fig. 10 of Kuo further discloses wherein a top surface of each of the second conductive lines (500) and the top surface of the second portion (portion of 206 in region 14) of the interlayer dielectric layer (206) are coplanar.
Regarding claim 5, Fig. 10 of Kuo discloses the semiconductor device according to claim 1 as applied above, and Fig. 10 of Kuo further discloses wherein a dielectric constant of the first dielectric layer (“The etching stop layer 602 may include dielectric materials such as silicon nitride (SiN)”, ¶ [0033]) is higher than a dielectric constant of the interlayer dielectric layer (“The dielectric material layer 206 may include dielectric materials such as silicon oxide (SiO.sub.2)”, ¶ [0024]).
Regarding claim 10, Fig. 10 of Kuo discloses the semiconductor device according to claim 1 as applied above, and Fig. 10 of Kuo further discloses wherein a dielectric constant of the first dielectric layer (602) ranges from 4 to 6 (“The etching stop layer 602 may include dielectric materials such as… silicon carbon nitride (SiCN)”, ¶ [0033]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220102621 A1) herein after “Wang621” in view of Wang et al. (US 20210035620 A1) herein after “Wang620”.
Regarding claim 1, Fig. 5 of Wang621 discloses a semiconductor device (Fig. 5, MRAM device, ¶ [0012]), comprising:
a device layer (“Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer 18”) comprising a first device region (Fig. 5, MRAM region 14, ¶ [0012]) and a second device region (Fig. 5, logic region 16, ¶ [0012]);
an interlayer dielectric layer (Fig. 5, IMD layer 58, ¶ [0018]) disposed above the device layer, wherein the interlayer dielectric layer (58) comprises:
a first portion (Fig. 5, portion of 58 in region 14) disposed above the first device region (14); and
a second portion (Fig. 5, portion of 58 in region 16) disposed above the second device region (16), wherein a top surface of the first portion (portion of 58 in region 14) is lower than a top surface of the second portion (portion of 58 in region 16) in a vertical direction;
a first interconnection structure (Fig. 5, metal interconnections 72 in region 14, ¶ [0022]) disposed corresponding to the first device region (14), wherein the first interconnection structure (72) comprises first conductive lines (72), and each of the first conductive lines (72) is partly located in the first portion (portion of 58 in region 14) of the interlayer dielectric layer (58);
a second interconnection structure (Fig. 5, metal interconnections 72 in region 16, ¶ [0022]) disposed corresponding to the second device region (16), wherein the second interconnection structure (72) comprises second conductive lines (72); and
a first dielectric layer (Fig. 5, nitride layer 62, ¶ [0019]) disposed on the first portion (portion of 58 in region 14) of the interlayer dielectric layer (58), wherein a part of the first dielectric layer (62) is sandwiched between two of the first conductive lines (72) adjacent to each other, and a bottom surface of the first dielectric layer (62) is lower than the top surface of the second portion (portion of 58 in region 16) of the interlayer dielectric layer (58) in the vertical direction.
Wang621 fails to disclose the second conductive lines located in the second portion of the interlayer dielectric layer.
In the similar field of endeavor of magnetoresistive random access memory devices, Fig. 7 of Wang620 discloses the second conductive lines (Fig. 7, lower via portion 604a, ¶ [0024]) located in the second portion of the interlayer dielectric layer (Fig. 7, portion of second dielectric layer 502 in region 14).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wang621 with the conductive lines as disclosed by Wang620, to ensure electrical connection (see Wang620, ¶ [0024]).
Regarding claim 6, Wang621 and Wang620 together disclose the semiconductor device according to claim 1 as applied above, and Fig. 5 of Wang621 further discloses comprising:
a second dielectric layer (Fig. 5, stop layer 68, ¶ [0021]) disposed on and contacting each of the first conductive lines (72), the first dielectric layer (62), each of the second conductive lines (72), and the second portion (portion of 58 in region 16) of the interlayer dielectric layer (58), wherein a dielectric constant of the second dielectric layer (68) is higher than a dielectric constant of the interlayer dielectric layer (58) (“layer 58 preferably include an ultra low-k (ULK) dielectric layer”, “the stop layer 68 could include silicon oxide, silicon nitride, or SiCN”, ¶ [0018] and [0021]).
Regarding claim 9, Wang621 and Wang620 together disclose the semiconductor device according to claim 6 as applied above, but the combination fails to explicitly disclose wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer.
However, it would have been obvious to one of ordinary skill in the art before the time of the effecting filing date of the invention to modify the first and second dielectric layers of Wang621 such that a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer through optimization of the production process within the prior art and/or because it has been ruled that changes of relative dimensions are prima facie obvious absent persuasive evidence that the particular configuration is significant, MPEP 2144.04(IV(A)).
Claims 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang621 (US 20220102621 A1) and Wang620 (US 20210035620 A1) in further view of Park et al. (US 20240213160 A1) herein after “Park”.
Regarding claim 7, Wang621 and Wang620 together disclose the semiconductor device according to claim 6 as applied above, but the combination fails to disclose wherein a material composition of the second dielectric layer is identical to a material composition of the first dielectric layer.
In the similar field of endeavor of semiconductor devices, Fig. 1 of Park discloses wherein a material composition of the second dielectric layer (Fig. 1, “The passivation layer 64 may include a silicon oxide layer”, ¶ [0059]) is identical to a material composition of the first dielectric layer (Fig. 1, “The second wiring insulating layer 40 may include a silicon oxide layer”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wang621 with the materials as disclosed by Park, to provide electrical insulating (see Park, ¶ [0107]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 11, Wang621 and Wang620 together disclose the semiconductor device according to claim 1 as applied above, but the combination fails to disclose wherein the first device region is a high voltage device region, and the second device region is a low voltage device region.
In the similar field of endeavor of semiconductor devices, Fig. 1 of Park discloses wherein the first device region is a high voltage device region (Fig. 1, high voltage region HVR, ¶ [0033]), and the second device region is a low voltage device region (Fig. 1, low voltage region LVR, ¶ [0033]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wang621 with the device regions as disclosed by Park, to provide the desired functionality (see Park, ¶ [0038]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yin (US 20220069201 A1) in view of Yang et al. (US 20230154922 A1) herein after “Yang”.
Regarding claim 15, Fig. 2A of Yin discloses the semiconductor device according to claim 12 as applied above, but Yin fails to disclose wherein the first device region is a high voltage device region, the second device region is a low voltage device region, and the third device region is a middle voltage device region.
In the similar field of endeavor of semiconductor devices, Fig. 35 of Yang discloses wherein the first device region is a high voltage device region (Fig. 35, “device region 100-HV for forming the HV transistor”, ¶ [0032]), the second device region is a low voltage device region (Fig. 35, “device region 100-LV for forming the LV transistor”, ¶ [0032]), and the third device region is a middle voltage device region (Fig. 35, “device region 100-MV for forming the MV transistor”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yin with the device regions as disclosed by Yang, to provide greater functionality (see Yang, ¶ [0019]).
Allowable Subject Matter
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior art of record fails to disclose or fairly suggest “each of the third conductive lines is partly located in the third portion of the interlayer dielectric layer,
another part of the first dielectric layer is sandwiched between two of the third conductive lines adjacent to each other, and a bottom surface of the first dielectric layer located on the third portion of the interlayer dielectric layer is lower than the top surface of the second portion of the interlayer dielectric layer” in combination with the other limitations of claim 13.
Regarding claim 14, claim 14 is dependent upon claim 13 and is allowable for at the same reasons.
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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