Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (20210057332).
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Regarding claim 17, Chen teaches an stacked structure, comprising:
a wafer (TC) having a first surface (bottom of bottom TC), a second surface (top of bottom TC) opposite to the first surface and a sidewall (sidewalls of bottom TC) connecting the first surface and the second surface;
semiconductor dies (10C) stacked on the second surface of the wafer and bonded to the wafer (please see above);
a filling material (IS1+IS2+IS3+ISN) disposed on the second surface of the wafer, filling between and wrapping around sidewalls of the semiconductor dies (please see above), and covering the sidewall of the wafer (please note that “cover” is taken to mean “to place over”; since IS1+IS2+IS3+ISN is placed over all of the bottom TC, IS1+IS2+IS3+ISN covers the TC),
wherein the stacked structure includes first die units (10B2) and second die units (10BT) connected with one another, the first die units are located in a bordering region of the wafer surrounding the second die units in an inner mid region of the wafer (please see figure above),
wherein the filling material covers the second surface and the sidewall of the wafer in the first die units (please see IS1+IS2+IS3+ISN does so to 10B2), while the filling material covers only the second surface of the wafer in the second die units (10BT can be seen only have the bottom surface covered by IS1+IS2+IS3+ISN and no other surface).
Regarding claim 18, Chen teaches an structure according to claim 17, further comprising a first bonding structure (20’) located on the wafer, wherein the first bonding structure includes a first bonding dielectric layer covering the second surface and the sidewall of the wafer and first bonding pads (150) embedded in the first bonding dielectric layer (please see 20’ which shows this arrangement).
Regarding claim 19, Chen teaches an structure according to claim 18, wherein the semiconductor dies include second bonding structures including second bonding dielectric layers (220; par. 40 teaches 220 being composed of silicon oxide layers) and second bonding pads (150) embedded in the second bonding dielectric layers, the second bonding dielectric layers are bonded with the first bonding dielectric layer, and the second bonding pads are bonded with the first bonding pads (all elements seen in the figured above are bonded to each other).
Regarding claim 20, Chen teaches an structure according to claim 17, wherein the filling material includes a main portion covering the sidewalls of the semiconductor dies and the second surface of the wafer, and a drape portion covering the sidewall of the wafer (please see above wherein IS1+IS2+IS3+ISN shows this).
Allowable Subject Matter
Claim1-16 allowed.
The following is an examiner’s statement of reasons for allowance: independent claims 1 and 10 recite a temporal ordering that is neither anticipated nor obviate by prior art..
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818