DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: Applicant amended in the content from claim 16 into each of claims 1, 11 and 17, but neglected to cancel claim 16 which depends from claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0294998 A1 to Lilak et al. (hereinafter “Lilak” – previously cited reference).
Regarding claim 1, Lilak discloses a semiconductor device (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]) comprising:
a first transistor comprising a first source/drain region disposed on a side of the first transistor (lower device region 104 having source/drain region 124A of a first transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a second transistor comprising a second source/drain region disposed on a side of the second transistor (lower device region 104 having source/drain region 124A of a second transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a first source/drain contact disposed under the first source/drain region, wherein sidewalls of the first source/drain contact are aligned with sidewalls of the first source/drain region (first backside source/drain contact 138 disposed under first source/drain region 124A with aligned sidewalls; Fig. 1A; paragraph [0013]); and
a second source/drain contact disposed under the second source/drain region, wherein a dimension of the second source/drain contact is larger than a dimension of the second source/drain region such that at least one sidewall of the second source/drain contact is out of alignment with at least one sidewall of the second source/drain region (second backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the second transistor comprises a plurality of channel layers contacting a dielectric layer of a gate cut portion at an edge where the at least one sidewall of the second source/drain contact is out of alignment with the at least one sidewall of the second source/drain region (nanowires 116A of second transistor disposed in contact with gate spacers 123 at edge sidewall of region 124A is out of alignment with contact 138 having feature 128, where gate spacers 123 are made from materials able to support an electrostatic field and exhibit a dielectric constant, where gate spacers 123 and isolation structure 324 are disposed between gate structures; Figs. 1A, 3A-3B; paragraphs [0019], [0045], [0052]).
Regarding claim 2, Lilak discloses the semiconductor device of claim 1, further comprising: a third transistor stacked on the first transistor and comprising a third source/drain region disposed on a side of the third transistor, wherein the third source/drain region is stacked on the first source/drain region (third transistor of upper device region 108 having source/drain region 124B stacked upon first source/drain region 124A; Fig. 1A; paragraph [0013]); and a fourth transistor stacked on the second transistor and comprising a fourth source/drain region disposed on a side of the fourth transistor, wherein the fourth source/drain region is stacked on the second source/drain region (fourth transistor of upper device region 108 having source/drain region 124B stacked upon second source/drain region 124A; Fig. 1A; paragraph [0013]).
Regarding claim 3, Lilak discloses the semiconductor device of claim 2, further comprising a via disposed along a side of the fourth source/drain region and the second source/drain region, wherein the at least one sidewall of the second source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 4, Lilak discloses the semiconductor device of claim 3, wherein the dielectric layer of the gate cut portion is disposed between the fourth source/drain region and the via, and between the second source/drain region and the via (gate spacers 123 and isolation structure 324 at least in part disposed between regions 124B and conductor 328 and between regions 124A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 5, Lilak discloses the semiconductor device of claim 3, wherein the fourth transistor comprises a plurality of channel layers contacting the dielectric layer of the gate cut portion (nanowires 116A of second transistor disposed in contact with gate spacers 123; Figs. 1A, 3A-3B; paragraph [0045]).
Regarding claim 6, Lilak discloses the semiconductor device of claim 5, the dielectric layer of the gate cut portion is disposed between the via and the plurality of channel layers of the second transistor and between the via and the plurality of channel layers of the fourth transistor (gate spacers 123 and isolation structure 324 at least in part disposed between nanowires 116B and conductor 328 and between nanowires 116A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 7, Lilak discloses the semiconductor device of claim 3, wherein: the via is connected to a voltage source disposed on a first side of the semiconductor device (buried conductor 328 may be electrically connected to a vertical interconnect which is electrically connected to frontside local contacts 125 and BEOL metallization layers M0-Mn which is the conventional way power and signals are delivered in ICs; Figs. 1A-1B, 3A-3B; paragraphs [0013], [0029], [0054]); and the first and the second source/drain contacts are disposed on a second side of the semiconductor device opposite the first side (contacts 138 and interconnect 128 disposed in backside contact region 103; Fig. 1A).
Regarding claim 8, Lilak discloses the semiconductor device of claim 7, wherein the first source/drain contact is connected to a voltage source disposed on the second side of the semiconductor device (backside contact region 103 including contacts 138 may utilize interconnects for connecting to voltage source to route power; Fig. 1A; paragraphs [0013], [0029], [0054]).
Regarding claim 9, Lilak discloses the semiconductor device of claim 1, wherein the first and the second source/drain contacts are disposed in a dielectric layer, and the first source/drain contact is disposed at a greater depth in the dielectric layer than the second source/drain contact (first contact 138 is disposed on average deeper within layer of dielectric materials 126, 136, 140 than second contact 138 with interconnect structure 128 which extends out of the dielectric layer; Fig. 1A).
Regarding claim 10, Lilak discloses the semiconductor device of claim 1, wherein the first transistor comprises a gate-all-around transistor, and the second transistor comprises a forksheet transistor (transistors may be gate-all-around transistors and may utilize centrally-disposed isolation wall structures as in a forksheet transistor; paragraphs [0008], [0029], [0042]).
Regarding claim 11, Lilak discloses a semiconductor device (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]) comprising:
a first transistor comprising a first source/drain region disposed on a side of the first transistor (lower device region 104 having source/drain region 124A of a first transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a second transistor stacked on the first transistor and comprising a second source/drain region disposed on a side of the second transistor, wherein the second source/drain region is stacked on the first source/drain region (second transistor of upper device region 108 having source/drain region 124B stacked upon first source/drain region 124A; Fig. 1A; paragraph [0013]); and
a source/drain contact disposed under the first source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the first source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the first source/drain region (first backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the first transistor comprises a plurality of channel layers contacting a dielectric layer of a gate cut portion at an edge where the at least one sidewall of the source/drain contact is out of alignment with the at least one sidewall of the first source/drain region (nanowires 116A of first transistor disposed in contact with gate spacers 123 at edge sidewall of region 124A is out of alignment with contact 138 having feature 128, where gate spacers 123 are made from materials able to support an electrostatic field and exhibit a dielectric constant, where gate spacers 123 and isolation structure 324 are disposed between gate structures; Figs. 1A, 3A-3B; paragraphs [0019], [0045], [0052]).
Regarding claim 12, Lilak discloses the semiconductor device of claim 11, further comprising a via disposed along a side of the second source/drain region and the first source/drain region, wherein the at least one sidewall of the source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 13, Lilak discloses the semiconductor device of claim 12, wherein the dielectric layer of the gate cut portion is disposed between the second source/drain region and the via, and between the first source/drain region and the via (gate spacers 123 and isolation structure 324 at least in part disposed between regions 124B and conductor 328 and between regions 124A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 14, Lilak discloses the semiconductor device of claim 12, wherein the second transistor comprises a plurality of channel layers contacting the dielectric layer of the gate cut portion, wherein the dielectric layer of the gate cut portion is disposed between the via and the plurality of channel layers of the second transistor (nanowires 116A of second transistor disposed in contact with gate spacers 123, where gate spacers 123 and isolation structure 324 at least in part disposed between nanowires 116B and conductor 328 and between nanowires 116A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 15, Lilak discloses the semiconductor device of claim 12, wherein: the via is connected to a voltage source disposed on a first side of the semiconductor device (buried conductor 328 may be electrically connected to a vertical interconnect which is electrically connected to frontside local contacts 125 and BEOL metallization layers M0-Mn which is the conventional way power and signals are delivered in ICs; Figs. 1A-1B, 3A-3B; paragraphs [0013], [0029], [0054]); and the source/drain contact is disposed on a second side of the semiconductor device opposite the first side (contacts 138 and interconnect 128 disposed in backside contact region 103; Fig. 1A).
Regarding claim 16, Lilak discloses the semiconductor device of claim 11, wherein the plurality of channel layers contact the dielectric layer of the gate cut portion where the at least one sidewall of the source/drain contact is out of alignment with the at least one sidewall of the first source/drain region (nanowires 116A of second transistor disposed in contact with gate spacers 123 at edge sidewall of region 124A is out of alignment with contact 138 having feature 128; Figs. 1A, 3A-3B; paragraph [0045]).
Regarding claim 17, Lilak discloses a semiconductor device comprising:
a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108, where gates 120 are alternately stacked with nanowires 116; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
at least one source/drain region disposed on a side of the stacked structure (lower device region 104 having source/drain region 124A on a side of alternately stacked nanowires 116 and gates 120; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]); and
a source/drain contact disposed under the at least one source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the at least one source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the at least one source/drain region (backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the plurality of channel layers contact a dielectric layer of a gate cut portion at an edge where the at least one sidewall of the source/drain contact is out of alignment with the at least one sidewall of the at least one source/drain region (nanowires 116A of transistor disposed in contact with gate spacers 123 at edge sidewall of region 124A is out of alignment with contact 138 having feature 128, where gate spacers 123 are made from materials able to support an electrostatic field and exhibit a dielectric constant, where gate spacers 123 and isolation structure 324 are disposed between gate structures; Figs. 1A, 3A-3B; paragraphs [0019], [0045], [0052]).
Regarding claim 18, Lilak discloses the semiconductor device of claim 17, further comprising a via disposed along a side of the at least one source/drain region, wherein the at least one sidewall of the source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 19, Lilak discloses the semiconductor device of claim 18, wherein the dielectric layer of the gate cut portion is disposed between the at least one source/drain region and the via (gate spacers 123 and isolation structure 324 at least in part disposed between regions 124B and conductor 328 and between regions 124A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 20, Lilak discloses the semiconductor device of claim 18, wherein the dielectric layer of the gate cut portion is disposed between the via and the plurality of gate structures and the plurality of channel layers (gate spacers 123 and isolation structure 324 at least in part disposed between conductor 328 and gate electrodes 120 and nanowires 116; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Response to Arguments
Applicant's arguments filed July 28, 2026 have been fully considered. Applicant provided amendments to claims 1, 11 and 17 along with corresponding arguments. Specifically, Applicant asserts that “proximity to” does not inherently include “contacting” when rebutting the previous 35 USC 103 rejection using Lilak. However, Examiner does not make such an assertion, but only asserts that the nanowires 116 of Lilak being in close proximity to the material 332 obviates the language requiring these structures to contact one another. In any event, this argument is moot given the alternate mapping of Lilak used in the current 35 USC 102 rejection using the same reference as outlined above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action (noting that while claim 16 was put into claim 11, the language further added “at an edge” allowing for a change in rejection based on the amendment). Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
