DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 22, 2023 is being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on December 20, 2023.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING AN IMPROVED PIXEL ELECTRODE AND METHOD OF MANUFACTURING THE SAME.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, and 9 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Tanaka (US 2023/0146966 A1).
Claim 1, Tanaka discloses a display device (display device 200a, [0163], Fig. 1) comprising:
a substrate (substrate 100, [0164], Fig. 1);
a pixel circuit layer (pixel 302 includes a pixel circuit layer, hereinafter, pixel circuit layer 302, [0207], Figs. 1 and 10) disposed on the substrate 100 and including at least one thin film transistor (offset area 126 operates as a thin film transistor, hereinafter, thin film transistor 126, [0091]; pixel circuit layer 302 includes a select transistor 136 and a drive transistor 138, [0207], Figs. 1 and 10); and
a pixel electrode (EL element 200 is a pixel electrode, hereinafter, pixel electrode 200, [0207], Figs. 1 and 10) disposed on the pixel circuit layer 302 and electrically connected to the at least one thin film transistor 136/138 (pixel electrode 200 is disposed on the pixel circuit layer 302 and electrically connected to the drive transistor 138, [0207], Figs. 1 and 10),
wherein the pixel electrode 200 comprises:
a lower layer (electron transport layer 106a is a lower layer, hereinafter, lower layer 106a, [0112], Fig. 1) including aluminum (lower layer 106a includes aluminum, [0112], Fig. 1),
an intermediate layer (second electron transport layer 106b is an intermediate layer, hereinafter, intermediate layer 106b, [0111], Fig. 1) disposed on the lower layer 106a and including a tungsten oxide (intermediate layer 106b is disposed on disposed on the lower layer 106a and includes tungsten oxide, [0111], Fig. 1), and
an upper layer (third electrode 118 is an upper layer, hereinafter, upper layer 118, [0137], Fig. 1) disposed on the intermediate layer 106b and including a transparent conductive oxide (upper layer 118 includes a transparent conductive oxide (i.e. indium tin oxide (ITO)), [0137], Fig. 1).
Claim 4, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 1.
Tanaka discloses wherein the upper layer 118 includes an indium tin oxide (ITO) (upper layer 118 includes indium tin oxide (ITO)), [0137], Fig. 1).
Claim 9, Tanaka discloses a display device (display device 200a, [0163], Fig. 1) comprising:
a substrate (substrate 100, [0164], Fig. 1);
a pixel circuit layer (pixel 302 includes a pixel circuit layer, hereinafter, pixel circuit layer 302, [0207], Figs. 1 and 10) disposed on the substrate 100 and including at least one thin film transistor (offset area 126 operates as a thin film transistor, hereinafter, thin film transistor 126, [0091]; pixel circuit layer 302 includes a select transistor 136 and a drive transistor 138, [0207], Figs. 1 and 10); and
a pixel electrode (EL element 200 is a pixel electrode, hereinafter, pixel electrode 200, [0207], Figs. 1 and 10) disposed on the pixel circuit layer 302 and electrically connected to the at least one thin film transistor 136/138 (pixel electrode 200 is disposed on the pixel circuit layer 302 and electrically connected to the drive transistor 138, [0207], Figs. 1 and 10),
wherein the pixel electrode 200 comprises:
a lower layer (electron transport layer 106a is a lower layer, hereinafter, lower layer 106a, [0112], Fig. 1) including aluminum (lower layer 106a includes aluminum, [0112], Fig. 1),
an intermediate layer (second electron transport layer 106b is an intermediate layer, hereinafter, intermediate layer 106b, [0111], Fig. 1) disposed on the lower layer 106a and including a tungsten oxide (intermediate layer 106b is disposed on disposed on the lower layer 106a and includes tungsten oxide, [0111], Fig. 1), and
an upper layer (third electrode 118 is an upper layer, hereinafter, upper layer 118, [0137], Fig. 1) disposed on the intermediate layer 106b and including an indium tin oxide (ITO) (upper layer 118 includes indium tin oxide (ITO), [0137], Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Kubota (US 2023/0309346 A1).
Claim 2, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 1.
Tanaka does not explicitly disclose wherein the lower layer includes an Al-Ti alloy.
However, Kubota discloses wherein the lower layer (Kubota, lower layer 111a/111b/111c/111d, [0199], Figs. 1A-1B; Tanaka, lower layer 106a, [0112], Fig. 1) includes an Al-Ti alloy (Kubota, lower layer 111a/111b/111c/111d may be formed of an alloy of aluminum and titanium (i.e. Al-Ti alloy), [0199], Figs. 1A-1B; Tanaka, lower layer 106a, [0112], Fig. 1). The combination to utilize an aluminum alloy underlying enables a high reflectivity of light underneath the subsequent conductive metal oxide films (Kubota, [0199]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an underlying aluminum alloy that enables a high reflectivity of light underneath the subsequent conductive metal oxide films (Kubota, [0199]).
Claim 6, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 1.
Tanaka does not explicitly disclose wherein the substrate is a semiconductor substrate including a semiconductor material.
However, Kubota discloses wherein the substrate (Kubota, substrate 101/102, [0224], Figs. 1A-1B; Tanaka, substrate 100, [0164], Fig. 1) is a semiconductor substrate including a semiconductor material (Kubota, substrate 101/102 includes a semiconductor material, [0224], Figs. 1A-1B; Tanaka, substrate 100, [0164], Fig. 1). The combination to utilize a substrate for a display device that is made of semiconductor material allows for the use of polarizing plates as well as increased substrate rigidity and light-transmission (Kubota, [0224]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a substrate for a display device that is made of semiconductor material allows for the use of polarizing plates as well as increased substrate rigidity and light-transmission (Kubota, [0224]).
Claim 12, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 9.
Tanaka does not explicitly disclose wherein the substrate is a semiconductor substrate including a semiconductor material.
However, Kubota discloses wherein the substrate (Kubota, substrate 101/102, [0224], Figs. 1A-1B; Tanaka, substrate 100, [0164], Fig. 1) is a semiconductor substrate including a semiconductor material (Kubota, substrate 101/102 includes a semiconductor material, [0224], Figs. 1A-1B; Tanaka, substrate 100, [0164], Fig. 1). The combination to utilize a substrate for a display device that is made of semiconductor material allows for the use of polarizing plates as well as increased substrate rigidity and light-transmission (Kubota, [0224]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a substrate for a display device that is made of semiconductor material allows for the use of polarizing plates as well as increased substrate rigidity and light-transmission (Kubota, [0224]).
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Wang (US 2023/0337451 A1).
Claim 5, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 1.
Tanaka does not explicitly disclose wherein a thickness of the upper layer is in a range of about 20 Å to about 100 Å.
However, Wang discloses wherein a thickness of the upper layer (Wang, upper layer is within first electrode and includes ITO, [0072], Fig. 3A; Tanaka, Fig. 1) is in a range of about 20 Å to about 100 Å (Wang, upper layer is between 75 Å to about 100 Å, [0072], Fig. 3A; Tanaka, Fig. 1). The combination to utilize an ITO layer in a thickness range of about 20 Å to about 100 Å allows for optimal reflectivity of the resultant material layer stack (Wang, [0072]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an ITO layer in a thickness range of about 20 Å to about 100 Å to allow for optimal reflectivity of the resultant material layer stack (Wang, [0072]).
Claim 11, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 9.
Tanaka does not explicitly disclose wherein a thickness of the upper layer is in a range of about 20 Å to about 100 Å.
However, Wang discloses wherein a thickness of the upper layer (Wang, upper layer is within first electrode and includes ITO, [0072], Fig. 3A; Tanaka, Fig. 1) is in a range of about 20 Å to about 100 Å (Wang, upper layer is between 75 Å to about 100 Å, [0072], Fig. 3A; Tanaka, Fig. 1). The combination to utilize an ITO layer in a thickness range of about 20 Å to about 100 Å allows for optimal reflectivity of the resultant material layer stack (Wang, [0072]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an ITO layer in a thickness range of about 20 Å to about 100 Å to allow for optimal reflectivity of the resultant material layer stack (Wang, [0072]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Park (US 2022/0199936 A1).
Claim 7, Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 1, further comprising:
a light-emitting layer (light emitting layer 112, [0090], Fig. 1) disposed on the pixel electrode 200 (light emitting layer 112 is disposed on the pixel electrode 200, [0090], Fig. 1).
Tanaka does not explicitly disclose a counter electrode disposed on the light-emitting layer; and a thin film encapsulation layer disposed on the counter electrode.
However, Park discloses a counter electrode (Park, second electrode CE is a counter electrode, hereinafter, counter electrode CE, [0101], Fig. 5; Tanaka, Fig. 1) disposed on the light-emitting layer (Park, counter electrode CE is disposed on the light-emitting layer EL, [0101], Fig. 5; Tanaka, Fig. 1); and a thin film encapsulation layer disposed on the counter electrode (Park, thin film encapsulation layer 170 is disposed on the counter electrode CE, [0102], Fig. 5; Tanaka, Fig. 1). The combination to utilize an upper electrode as well as a thin film encapsulation layer prevents external air and moisture from permeating into the resultant display device (Park, [0102]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an upper electrode as well as a thin film encapsulation layer to prevent external air and moisture from permeating into the resultant display device (Park, [0102]).
Claim 8, Tanaka/Park discloses the display device (Tanaka, display device 200a, [0163], Fig. 1; Park, display device, [0034], Figs. 1 and 5) of claim 7.
Tanaka/Park further comprising a red color filter, a green color filter, and a blue color filter disposed on the thin film encapsulation layer (Tanaka, each light emitting layer 112 is further covered with a predetermined color material, [0288], Fig. 1; Park, each pixel is defined by the color filter layer to achieve red light, green light, and blue light, [0100], Fig. 5).
Allowable Subject Matter
Claims 13-20 are allowed.
Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Tanaka (US 2023/0146966 A1), Kubota (US 2023/0309346 A1), Park (US 2022/0199936 A1), Wang (US 2023/0337451 A1), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 3, in the Al-Ti alloy, an atomic ratio of titanium (Ti) has a range of about 0.01 at% to about 0.1 at%.
Regarding claim 10, in the Al-Ti alloy, an atomic ratio of titanium (Ti) has a range of about 0.01 at% to about 0.1 at%.
Tanaka discloses the display device (display device 200a, [0163], Fig. 1) of claim 9, wherein
Tanaka does not explicitly disclose wherein the lower layer includes an Al-Ti alloy.
However, Kubota (US 2023/0309346 A1) discloses wherein the lower layer (Kubota, lower layer 111a/111b/111c/111d, [0199], Figs. 1A-1B; Tanaka, lower layer 106a, [0112], Fig. 1) includes an Al-Ti alloy (Kubota, lower layer 111a/111b/111c/111d may be formed of an alloy of aluminum and titanium (i.e. Al-Ti alloy), [0199], Figs. 1A-1B; Tanaka, lower layer 106a, [0112], Fig. 1). The combination to utilize an aluminum alloy underlying enables a high reflectivity of light underneath the subsequent conductive metal oxide films (Kubota, [0199]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an underlying aluminum alloy that enables a high reflectivity of light underneath the subsequent conductive metal oxide films (Kubota, [0199]).
Tanaka/Kubota does not explicitly disclose the following limitations; in the Al-Ti alloy, an atomic ratio of titanium (Ti) has a range of about 0.01 at% to about 0.1 at%.
Regarding claim 13 (from which claims 14-20 depend), forming a pixel electrode including a lower layer, an intermediate layer, and an upper layer by dry etching the preliminary lower conductive layer, the preliminary intermediate conductive layer, and the preliminary upper conductive layer.
Tanaka discloses a method of manufacturing a display device (display device 200a, [0163], Fig. 1), the method comprising:
forming, on a substrate (substrate 100, [0164], Fig. 1), a pixel circuit layer (pixel 302 includes a pixel circuit layer, hereinafter, pixel circuit layer 302, [0207], Figs. 1 and 10) including at least one thin film transistor (offset area 126 operates as a thin film transistor, hereinafter, thin film transistor 126, [0091]; pixel circuit layer 302 includes a select transistor 136 and a drive transistor 138, [0207], Figs. 1 and 10);
forming, on the pixel circuit layer, a preliminary lower conductive layer (electron transport layer 106a is a lower layer, hereinafter, lower layer 106a, [0112], Fig. 1) electrically connected to the at least one thin film transistor and including aluminum (lower layer 106a includes aluminum, [0112], Fig. 1);
forming, on the preliminary lower conductive layer 106a, a preliminary intermediate conductive layer (second electron transport layer 106b is an intermediate layer, hereinafter, intermediate layer 106b, [0111], Fig. 1) including a tungsten oxide (intermediate layer 106b is disposed on disposed on the lower layer 106a and includes tungsten oxide, [0111], Fig. 1);
forming, on the preliminary intermediate conductive layer 106b, a preliminary upper conductive layer (third electrode 118 is an upper layer, hereinafter, upper layer 118, [0137], Fig. 1) including a transparent conductive oxide (upper layer 118 includes a transparent conductive oxide (i.e. indium tin oxide (ITO)), [0137], Fig. 1).
Tanaka/Kubota does not explicitly disclose the following limitations; forming a pixel electrode including a lower layer, an intermediate layer, and an upper layer by dry etching the preliminary lower conductive layer, the preliminary intermediate conductive layer, and the preliminary upper conductive layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812