DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed August 10, 2026, has been entered. Claims 1-5, 7-10, and 12-20 remain pending in the application. Claims 4, 9-10, and 12-20 remain withdrawn as being drawn to a nonelected Group and Species.
Claim Objections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et. al. (WO 2021054551 A1, using US 20220376144 A1 for ease of reference), hereinafter An.
Regarding claim 1, An teaches a light emitting element (Fig 20 light emitting element 300_1, [0220]) comprising: a first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]); a second semiconductor layer (Fig 20 a first semiconductor layer 310_1, [0222]); an active layer (Fig 20 active layer 330_1, [0222]) between (Fig 20) the first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]) and the second semiconductor layer (Fig 20 a first semiconductor layer 310_1, [0222]) in a stacking direction (Fig 20 up/down direction); a first insulating layer (Fig 20 insulating film 380_1,[0220]) surrounding (Fig 20) the first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]), the second semiconductor layer (Fig 20 a first semiconductor layer 310_1, [0222]), and the active layer (Fig 20 active layer 330_1, [0222]); and an electrode layer (Fig 20 electrode layer 370_1, [0221]) on (the bottom surface of the electrode layer is on the top surface of the first semiconductor layer; the side surface of the electrode layer is on the side surface of the first insulating layer; the electrode layer Is on both of these structures while also being in the stacking direction; the claim as written does not require the bottom surface of the electrode layer to be on both the first semiconductor layer and first insulating layer in the stacking direction) the first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]) and the first insulating layer (Fig 20 insulating film 380_1,[0220]) in the stacking direction (Fig 20 up/down direction), wherein a first thickness (Fig 20 second thickness W2, [0224]) of the first insulating layer (Fig 20 insulating film 380_1,[0220]) surrounding the first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]) is different ([0224]) from a second thickness (Fig 20 third thickness W3, [0224]) of the first insulating layer (Fig 20 insulating film 380_1,[0220]) surrounding the second semiconductor layer (Fig 20 a first semiconductor layer 310_1, [0222]).
Regarding claim 2, An teaches the first thickness (Fig 20 second thickness W2, [0224]) of the first insulating layer (Fig 20 insulating film 380_1,[0220]) is thinner (W3 may be greater than W2, [0224]) than the second thickness (Fig 20 third thickness W3, [0224]) of the first insulating layer (Fig 20 insulating film 380_1,[0220]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et. al. (WO 2021054551 A1, using US 20220376144 A1 for ease of reference), hereinafter An, with supporting evidence from Lee et. al. (US 20210296537 A1), hereinafter Lee.
An fails to teach a diameter of the first semiconductor layer (Fig 20 second semiconductor layer 320_1, [0221]) and a diameter of the second semiconductor layer (Fig 20 a first semiconductor layer 310_1, [0222]) are same as each other.
However, Lee teaches a light emitting element (Fig 1B light emitting element LD, [0065]) with a rod shape similar to An with a diameter marked (Fig 1B diameter D, [0065]). Lee does not show additional markings to indicate the diameter changes along the length of the rod shape. Thus, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the diameter of the first and second semiconductor layers of An would be the same as each other. MPEP 2131.01(III)
Claims 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over An et. al. (WO 2021054551 A1, using US 20220376144 A1 for ease of reference), hereinafter An, in view of Cho et. al. (US 20210167050 A1), hereinafter Cho
Regarding claim 5, An fails to teach a second insulating layer surrounding the first insulating layer.
However, Cho teaches a second insulating layer (Fig 4 second insulating layer 382, [0123]) surrounding the first insulating layer (Fig 4 first insulating layer 381, [0123] corresponding to An: Fig 20 insulating film 380_1,[0220]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified An to incorporate the teachings of Cho by having a second insulating layer surrounding the first insulating layer. This would protect the first insulating layer during later processing steps ([0123]).
Regarding claim 7, An as modified in claim 5 teaches the second insulating layer (Cho: Fig 4 second insulating layer 382, [0123]) surrounds a side surface (Cho: See note below) of the electrode layer (An: Fig 20 electrode layer 370_1, [0221]).
Examiner notes the second insulating layer surrounds the first insulating layer after processing to expose the top of the light emitting element, as shown in Figs 12-15 of Cho; The exposed electrode layer of An would be surrounded by the second insulating layer in the process of Cho.
Regarding claim 8, An as modified in claim 5 teaches the second insulating layer (Cho: Fig 4 second insulating layer 382, [0123]) exposes (Cho: Fig 16) the electrode layer (Cho: Fig 16 electrode material layer 370 corresponds to An: Fig 20 electrode layer 370_1, [0221]) and the second semiconductor layer (Cho: Fig 16 first conductivity type semiconductor 310, [0122] corresponds to An: Fig 20 a first semiconductor layer 310_1, [0222]).
Response to Arguments
Applicant's arguments, see 35 USC §102/103 section starting on page 7, filed August 10, 2026, with respect to the amendments to claim 1 not being taught, have been fully considered but they are not persuasive.
The claim as written can be interpreted in the manner used in the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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