DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Merilo et al. (U.S. Publication No. 2007/0210443).
Regarding claim 1, Merilo teaches a chip package structure, comprising:
a circuit substrate (Fig. 3, substrate 110);
a lead frame (lead frame 214) stacked on the circuit substrate, wherein the lead frame is bent to form an accommodating space (see Fig. 3, space where chips are located);
a first chip (chip 106, labeled in Fig. 1-2) disposed on the lead frame (Fig. 3), wherein the first chip is located in the accommodating space (Fig. 3);
a second chip (chip 112) disposed on the circuit substrate, wherein the second chip is located in the accommodating space (Fig. 3);
a connecting member (unshown connection between extended leads 202 and substrate 110; see paragraph [0038]) connecting member connected to the lead frame and the circuit substrate (Fig. 3); and
a package body (package body 314) disposed on the circuit substrate, wherein the package body covers the second chip and the lead frame (Fig. 3).
Regarding claim 3, Merilo teaches the chip package structure according to claim 1, wherein the 3lead frame includes a first frame (see Fig. 2, first frame 202), a second frame (also labeled 202), and a third frame (204), the third frame is disposed between the first frame and the second frame (see Fig. 2), the third frame includes an outer surface and an inner surface (see Fig. 2-3), the first chip is disposed on the inner surface, and the outer surface is exposed from the package body (see Fig. 3).
Regarding claim 7, Merilo teaches the chip package structure according to claim 3, further including a first metal wire (Merilo Fig. 2-3, first wire 208) and a second metal wire (also labeled 208), wherein the first metal wire is used to connect the first chip and the first frame (Fig. 2-3), and the second metal wire is used to connect the first chip and the second frame (Fig. 2-3).
Regarding claim 12, Merilo teaches the chip package structure according to claim 1, wherein the circuit substrate is a laminated printed circuit board structure (see Fig. 3, substrate is several laminated layers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Merilo in view of Kao et al. (U.S. Publication No. 2019/0109064)
Regarding claim 2, Merilo teaches the chip package structure according to claim 1, wherein the first chip is a power integrated circuit chip, and the second chip is a driver integrated circuit chip.
However, Kao teaches that the chips in a multi-chip lead frame package can be a power chip and a driving chip (see Kao paragraphs [0025] and [0030]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the generic chips of Merilo could have been the specific chip types of Kao because it would have been a simple substitution of one known chip type for another and because Kao teaches that this combination of chips is useful for motor applications (see Kao paragraph [0003]).
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Merilo in view of Bathan et al. (U.S. Publication No. 2009/0230517)
Regarding claim 4, Merilo teaches the chip package structure according to claim 3, wherein the circuit substrate includes a plurality of metal pads (not shown, but inherent that pads are located on the top surface in order for connections to be possible), the plurality of metal pads include a first metal pad (unshown pad where 202 connects), a second metal pad (unshown pad where 202 connects), and a third metal pad (unshown pad where 310 connects), and the second chip is disposed on the third metal pad (see Fig. 3, second chip connects at 310 pad).
Merilo does not specifically teach that solder is used to connect the first frame to the first pad, and second frame to the second pad. However, Bathan teaches a similar package in which the leads are connected to the substrate with solder (Bathan Fig. 2, solder 110 connects leads 102 to substrate 202). It would have been obvious to a person of skill in the art at the time of the effective filing date that solder could have been used to connect the leads and substrate of Merilo because solder is the most common form of electrically coupling parts in semiconductor packages and it would have been a simple substitution of the unknown material of Merilo for the known material of Bathan.
Regarding claim 13, Merilo teaches the chip package structure according to claim 1, wherein the circuit substrate is made of ceramic.
However, Bathan teaches that a similar substrate in a similar package can be ceramic (bathan paragraph [0037]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the substrate could have been ceramic because it would have been a simple substitution of one known substrate material for another with predictable results.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Merilo in view of Bathan, further in view of Hatori et al. (U.S. Publication No. 2020/0411419)
Regarding claim 5, Merilo in view of Bathan teaches the chip package structure according to claim 4, wherein the first solder and the second solder are made of tin.
However, Hatori teaches that solder used for leads can be tin based (see Hatori paragraph [0100]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the solder of Merilo in view of Bathan could have used tin solder because it would have been a simple substitution of one solder type for another with predictable results.
Regarding claim 6, Merilo in view of Bathan teaches the chip package structure according to claim 4, wherein the first solder and the second solder are made of copper core solder balls.
However, Hatori teaches that solder used for leads can be copper core based (see Hatori paragraph [0100]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the solder of Merilo in view of Bathan could have used copper core solder because it would have been a simple substitution of one solder type for another with predictable results.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Merilo in view of Bathan, further in view of Railkar et al. (U.S. Publication No. 2010/0193942).
Regarding claim 8, Merilo in view of Bathan teaches the chip package structure according to claim 4, wherein the lead frame further includes a heat dissipating element, and the heat dissipating element is embedded into the third frame.
However, Railkar teaches a similar lead frame in which the central die pad/frame portion has an embedded heat dissipating element (see Railkar Fig. 4, thermal spreader 480 embedded in central frame portion 440). It would have been obvious to a person of skill in the art at the time of the effective filing date that a heat dissipating element could have been embedded in the central frame of Merilo as well because this allows for improved heat shedding, which is important for chip efficiency and life)
Regarding claim 9, Merilo in view of Bathan and Railkar teaches the chip package structure according to claim 8, wherein the heat dissipating element protrudes from a side of the third frame (protrudes from the top side in the orientation of Railkar Fig. 4).
Regarding claim 10, Merilo in view of Bathan and Railkar teaches the chip package structure according to claim 9, wherein the heat dissipating element is made of ceramic (Railkar paragraph [0066]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Merilo in view of Bathan, further in view of Yuan et al. (CN 109148411).
Regarding claim 11, Merilo in view of Bathan teaches the chip package structure according to claim 4, wherein the circuit substrate includes at least one heat dissipating element, and the at least one heat dissipating element is embedded into the circuit substrate and contacts one of the metal pads.
However, Yuan teaches another substrate which as a heat dissipating element embedded into the substrate and contacting the metal pads (see Yuan Fig. 1, dissipating member 20 embedded in substrate and contacting pads 10). It would have been obvious to a person of skill in the art at the time of the effective filing date that a similar heat dissipating member could have been embedded into the substrate of Merilo because this allows for superior heat shedding, improving chip efficiency and life.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVAN G CLINTON/ Primary Examiner, Art Unit 2899