DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 1-12 in the reply filed on 05/20/2026 is acknowledged.
The examiner acknowledges the addition of new claims 21-28.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/01/2024 is being considered by the examiner.
Drawings
The drawings submitted on 02/16/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 26 and 27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 20220052009 A1).
Regarding claim 26, Huang discloses a method comprising:
forming a first through-via (174) and a second through-via (another 174) penetrating through a semiconductor substrate (172);
forming a redistribution structure (176) comprising:
a plurality of dielectric layers (178) over the semiconductor substrate (172); ([0046], Fig. 8) and
a plurality of metal lines (180) in the plurality of dielectric layers (178); ([0046], Fig. 8) and
when the redistribution structure (176) is formed, forming a plurality of dummy patterns (180B) in the plurality of dielectric layers (178), wherein in a top view (see Fig. 16A) of the redistribution structure (under 50 and 100 of Fig. 16A), the plurality of dummy patterns (180B) are between the first through-via (under 50 on the left side of Fig. 16A) and the second through-via (under 50 on the right side of Fig. 16A), and wherein from regions (Zone 3) closer to the first through-via or the second through-via (under 50) to a middle region (Zone 1) between the first through-via and the second through-via (under 50), pattern densities (widths of 180B) of the plurality of dummy patterns (180B) increase. (Fig. 16A)
Regarding claim 27, Huang discloses the method of claim 26, wherein the middle region (Zone 1) between the first through-via (under 50 on the left of Fig. 16A) and the second through-via (under 50 on the right side of Fig. 16A) has a highest pattern density of dummy patterns. (Fig. 16A)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20110248404 A1).
Regarding claim 1, Chiu discloses a method comprising:
forming an integrated circuit device (26) on a semiconductor substrate (12); ([0013], Fig. 3)
forming a first through-via (20B) penetrating through the semiconductor substrate (12); ([0017], Fig. 3) and
forming dummy patterns (28B, 30B, 40B and 68B, 70B, 74B) surrounding the first through-via (20B), ([0014], Fig. 3)
Chiu does not explicitly disclose:
wherein the dummy patterns comprise:
a first plurality of dummy patterns having a first pattern density; and
a second plurality of dummy patterns, wherein the first plurality of dummy patterns are between the first through-via and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density.
However, Chiu shows:
wherein the dummy patterns (at least 28B, 30B, 40B) comprise:
a first plurality of dummy patterns (30B) having a first pattern density (smaller width); and
a second plurality of dummy patterns (28B), wherein the first plurality of dummy patterns are (vertically) between the first through-via (20B) and the second plurality of dummy patterns (28B), and wherein the second plurality of dummy patterns (28B) have a second pattern density (medium width as shown in Figure 3) different from the first pattern density (smaller width as shown in Fig. 3).
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Chiu for the dummy patterns comprise: a first plurality of dummy patterns having a first pattern density; and a second plurality of dummy patterns, wherein the first plurality of dummy patterns are between the first through-via and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density so that “pattern-loading effect in the formation of metal lines 28, vias 30, and metal pads 40 is reduced.” (Chiu, [0016])
Regarding claim 2, Chiu discloses the method of claim 1, wherein the dummy patterns (at least 28B, 30B, 40B) further comprise a third plurality of dummy patterns (40B), with the first plurality of dummy patterns (30B) and the second plurality of dummy patterns (28B) being (vertically) between the first through-via (20B) and the third plurality of dummy patterns (40B), wherein the third plurality of dummy patterns have a third pattern density (larger width) different from both of the first pattern density (smaller width as shown in Fig. 3) and the second pattern density (medium width as shown in Fig. 3). ([0015], Fig. 3)
Chiu does not explicitly disclose having a plurality of the third dummy patterns however, it would be obvious to include a plurality of third dummy patterns 40B because “FIG. 1 illustrates a portion of semiconductor chip 10,” per [0013] which leads the examiner to believe there would be a plurality of third dummy patterns in a finished semiconductor device.
Regarding claim 3, Chiu discloses the method of claim 2, wherein the third pattern density (larger width as shown in Fig. 3) is greater than the second pattern density (medium width as shown in Fig. 3), and the second pattern density is greater than the first pattern density (smaller width as shown in Fig. 3).
Regarding claim 4, Chiu discloses the method of claim 1, wherein the forming the first through-via (20B) comprises:
forming the first through-via (20B) extending into the semiconductor substrate (12); ([0017], Fig. 1)
performing a backside grinding process (per [0019]) to reveal the first through-via (20B) from a backside of the semiconductor substrate (12); (Fig. 2) and
forming a backside interconnect structure (60) on the backside of the semiconductor substrate (12). ([0020], Fig. 3)
Regarding claim 5, Chiu discloses the method of claim 4 further comprising forming additional dummy patterns (68B, 70B, 74B) on the backside of the semiconductor substrate (12), wherein the additional dummy patterns (68B, 70B, 74B) have a lower pattern density in a (vertical) region closer to the first through-via (20B), and a higher pattern density in a (vertical) region farther away from the first through-via (20B). ([0020], Fig. 3)
Regarding claim 8, Chiu discloses the method of claim 1, wherein the first through-via (20B) is formed through a via-last process (per [0017]), and is formed after both of the integrated circuit device (26) and the dummy patterns (28B, 30B, 40B) are formed. (Fig. 3)
Regarding claim 10, Chiu discloses the method of claim 1, wherein the dummy patterns (28B, 30B, 40B) are electrically floating. (per [0016], Fig. 3)
Regarding claim 11, Chiu discloses the method of claim 1. Chiu does not disclose wherein the first plurality of dummy patterns have different shapes than the second plurality of dummy patterns.
However, it would be obvious to one skilled in the art before the effective filing date to use the teachings of Chiu and change the shape of the dummy patterns since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding claim 12, Chiu discloses the method of claim 1, wherein the first plurality of dummy patterns (30B) have different spacings than the second plurality of dummy patterns (28B). (Fig. 3)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20110248404 A1) as applied to claim 1 above, and further in view of Chen et al. (US 20210391413 A1).
Regarding claim 6, Chiu discloses the method of claim 1. Chiu does not disclose wherein each of the first pattern density and the second pattern density is measured in chip areas with both of lengths and widths greater than about 50 µm.
However, Chen discloses:
wherein each of the first pattern density (225) and the second pattern density (235) is measured in chip areas with both of lengths and widths greater than about 50 µm. ([0033], [0035], Fig. 8A and 9A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chiu and Chen for the first pattern density and the second pattern density is measured in chip areas with both of lengths and widths greater than about 50 µm so that “a manufacturing cost of the semiconductor structure is reduced” (Chen, [0036])
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20110248404 A1) as applied to claim 1 above, and further in view of Lin et al. (US 20210082846 A1).
Regarding claim 7, Chiu discloses the method of claim 1, wherein the first through-via is formed through a via- middle process, and is formed after the integrated circuit device is formed, and before the dummy patterns are formed.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20110248404 A1) as applied to claim 1 above, and further in view of Hu et al. (US 20220012402 A1).
Regarding claim 9, Chiu discloses the method of claim 1.Chis does not disclose further comprising, when the first through-via is formed, forming a second through-via, wherein the dummy patterns further comprise:
a fourth plurality of dummy patterns having a fourth pattern density;
a fifth plurality of dummy patterns having a fifth pattern density between the second through-via and the fourth plurality of dummy patterns; and
a sixth plurality of dummy patterns having a sixth pattern density between the fifth plurality of dummy patterns and the second plurality of dummy patterns, wherein the fifth pattern density is greater than the fourth pattern density, and the sixth pattern density is greater than the fifth pattern density.
However, Hu discloses:
when the first through-via (200) is formed, forming a second through-via (other 200), wherein the dummy patterns (208, 210, 302) further comprise:
a fourth plurality of dummy patterns (208) having a fourth pattern density (annotated below);
a fifth plurality of dummy patterns (210) having a fifth pattern density (annotated below) between the second through-via and the fourth plurality of dummy patterns; and
a sixth plurality of dummy patterns (302) having a sixth pattern density (annotated below) between the fifth plurality of dummy patterns and the second plurality of dummy patterns, wherein the fifth pattern density is greater than the fourth pattern density, and the sixth pattern density is greater than the fifth pattern density. (Fig. 6)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chiu and Hu for the dummy patterns further comprise: a fourth plurality of dummy patterns having a fourth pattern density; a fifth plurality of dummy patterns having a fifth pattern density between the second through-via and the fourth plurality of dummy patterns; and a sixth plurality of dummy patterns having a sixth pattern density between the fifth plurality of dummy patterns and the second plurality of dummy patterns, wherein the fifth pattern density is greater than the fourth pattern density, and the sixth pattern density is greater than the fifth pattern density so that “non-uniform loading effects on the active devices corresponding to active regions 206 during manufacturing processes may be reduced. As a result, performance loss of active devices may be prevented.” (Hu, [0035])
Claims 21, 22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 20150348872 A1) and in view of Chiu et al. (US 20110248404 A1).
Regarding claim 21, Kuo discloses a method comprising:
forming a first interconnect structure (per [0032]) overlying a semiconductor substrate(100);
etching the first interconnect structure (per [0015]) and the semiconductor substrate (100) to form an opening (140); ([0014], Fig. 2)
forming a through-via (160) in the opening and penetrating through the semiconductor substrate (110); ([0023])
forming a first dummy pad region (180) encircling the through-via (160), wherein the first dummy pad region comprises first dummy patterns having a first pattern density (smaller width); (Fig.
when the first dummy pad region (180) is formed, forming a second dummy pad region (190) encircling the first dummy pad region (180), wherein the second dummy pad region comprises second dummy patterns having a second pattern density (larger width) different from the first pattern density; (Fig. 4)
Kuo does not disclose:
forming a second interconnect structure, wherein the first interconnect structure and the second interconnect structure are on opposite sides of the semiconductor substrate, and wherein the through-via electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure.
However, Chiu discloses:
forming a second interconnect structure (60), wherein the first interconnect structure (26) and the second interconnect structure (60) are on opposite sides of the semiconductor substrate (12), and wherein the through-via (20A) electrically connects a first metal pad (28A) in the first interconnect structure (26) to a second metal pad in the second interconnect structure (60). (Fig. 3)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kuo and Chiu for forming a second interconnect structure, wherein the first interconnect structure and the second interconnect structure are on opposite sides of the semiconductor substrate, and wherein the through-via electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure in order to “integrate multiple chips into a single device” (Chiu, [0001])
Regarding claim 22, Kuo discloses the method of claim 21, wherein the first dummy pad region (180) has a substantially uniform pattern density of the first dummy patterns (180), and the second dummy pad region (190) has a substantially uniform pattern density of the second dummy patterns (190). (Fig. 5)
Regarding claim 24, Kuo discloses the method of claim 21 further comprising forming active devices (170) at a top surface of the semiconductor substrate (110), wherein the first dummy patterns (180) and the second dummy patterns (190) are over the semiconductor substrate (110). ([0023], Fig. 4)
Regarding claim 25, Kuo discloses the method of claim 21 further comprising forming active devices (170) at a top surface of the semiconductor substrate (110).
Kuo does not disclose:
wherein the first dummy patterns and the second dummy patterns are under the semiconductor substrate.
However, Chiu discloses:
wherein the first dummy patterns (70B) and the second dummy patterns (68B) are under the semiconductor substrate (12). (Fig. 3)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kuo and Chiu for the first dummy patterns and the second dummy patterns are under the semiconductor substrate because “with the formation of dummy metal lines and dummy vias on the backside of wafer 10, the formation of backside interconnect structure 60 suffers less from pattern-loading effects. Further, the dummy metal lines and dummy vias on the backside of wafer 10 may be connected to the dummy metal lines and dummy vias on the front side of wafer 10 to form an integrated metal feature. As a result, the likelihood of dielectric peeling between dielectric layers 32 and 72 is reduced, and hence the strength of wafer 10 may be improved.” (Chiu, [0023])
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 20150348872 A1) and in view of Chiu et al. (US 20110248404 A1 as applied to claim 21 above, and further in view of Hu et al. (US 20220012402 A1).
Regarding claim 23, Kuo in view of Chiu disclose the method of claim 21. Kuo in view of Chiu do not disclose further comprising forming a third dummy pad region encircling the second dummy pad region, wherein the third dummy pad region comprises third dummy patterns having a third pattern density different from both of the first pattern density and the second pattern density.
However, Hu discloses:
a third dummy pad region (302) encircling the second dummy pad region (206), wherein the third dummy pad region (302) comprises third dummy patterns (annotated below) having a third pattern density different from both of the first pattern density (annotated below) and the second pattern density (annotated below). (Fig. 6)
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It would have been obvious to one skilled in the art before the effective filing to combine the teachings of Kuo and Chiu in view of Hu for forming a third dummy pad region encircling the second dummy pad region, wherein the third dummy pad region comprises third dummy patterns having a third pattern density different from both of the first pattern density and the second pattern density so that “non-uniform loading effects on the active devices corresponding to active regions 206 during manufacturing processes may be reduced. As a result, performance loss of active devices may be prevented.” (Hu, [0035])
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 20220052009 A1) as applied to claim 26 above, and further in view of Chen et al. (US 20210391413 A1).
Regarding claim 28, Huang discloses the method of claim 26. Huang does not disclose wherein the pattern densities of the plurality of dummy patterns are measured from device regions with length and width greater than about 50 pm.
However, Chen discloses:
wherein each of the first pattern density (225) and the second pattern density (235) is measured in chip areas with both of lengths and widths greater than about 50 µm. ([0033], [0035], Fig. 8A and 9A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chiu and Chen for the first pattern density and the second pattern density is measured in chip areas with both of lengths and widths greater than about 50 µm so that “a manufacturing cost of the semiconductor structure is reduced” (Chen, [0036])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al. (US 20220310527 A1) discloses “forming patterned dummy features and/or dummy overlays useful in, for example, producing semiconductor devices with aligned metallization layers. Embodiments of forming the dummy overlays may be directed towards identifying pattern densities of neighboring local areas within a metallization layer and providing a uniformity of pattern densities between the neighboring local areas. In some embodiments, a dummy insertion structure is formed within a first local area having a relatively low pattern density as compared to a pattern density of a second local area, the second local area being a neighboring local area to the first local area” in paragraph [0016] and “warpage bias vs. pattern densities of the semiconductor dies” in [0067] but does not disclose all features as required by the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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