DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/19/2024, 9/24/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-16 are rejected under 35 U.S.C. 112(b)
In claim 9, lines 22-23, the limitation “the second fin-shaped structure” renders the claim indefinite because the antecedent basis is unclear as to whether “the second fin-shaped structure” refers to “a second fin-shaped structure” or “a third fin-shaped structure” previously recited in claim 9, on at least lines 4-5. Applicant’s specification [0026] and figure 8 describe that the second opening 2260 removes the second fin-shaped structure 210. Therefore, it is suggested Applicant change “the second fin-shaped structure” in claim 9, lines 22-23 to “the third fin-shaped structure”. For examination purposes, the limitation will be interpreted and examined as “the third fin-shaped structure” recited in claim 9. Correction is requested.
Claims 10-16 are also rejected as being dependent on claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 2020/0411661).
Regarding claim 1, Guler discloses, in at least figures 1A-1B and related text, a semiconductor structure, comprising:
a substrate (102, [24]);
a first base fin (left 105, [24], figures) and a second base fin (middle 105, [24], figures) arising from the substrate (102, [24]);
an isolation structure (106, [24]) disposed between the first base fin (left 105, [24], figures) and the second base fin (middle 105, [24], figures) along a direction (horizontal direction, figures);
a first plurality of channel members (107, [25]) disposed over the first base fin (left 105, [24], figures);
a second plurality of channel members (107, [25]) disposed over the second base fin (middle 105, [24], figures);
a region isolation feature (120/199 between 170A and 170B, [28], figures) extending through the isolation structure (106, [24]);
a first gate structure (108 of 170A, [30]) wrapping around each of the first plurality of channel members (107, [25]);
a second gate structure (108 of 170B, [31]) wrapping around each of the second plurality of channel members (107, [25]);
a first gate cut feature (121B, [28]) extending through the first gate structure (108 of 170A, [30]) and into the isolation feature (106, [24]); and
a second gate cut feature (120, [28]) extending though the second gate structure (108 of 170B, [31]) and into the isolation feature (106, [24]),
wherein, along the direction (horizontal direction, figures), each of the first gate cut feature (121B, [28]) and the second gate cut feature (120, [28]) are spaced apart from the region isolation feature (120/199 between 170A and 170B, [28], figures).
Guler does not explicitly disclose a region isolation feature extending into the substrate.
Chen teaches, in at least figures 15A-15C and related text, the device comprising a region isolation feature (50/66, [41]) extending into the substrate (20, [37]), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Guler and Chen are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guler with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guler to have the region isolation feature extending into the substrate, as taught by Chen, for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43], Chen).
Regarding claim 2, Guler in view of Chen discloses the semiconductor structure of claim 1 as described above.
Guler further discloses, in at least figures 1A-1B and related text, the first gate structure (108 of 170A, [30]) comprises a first gate dielectric layer (152, [28]) and a first gate electrode layer (150, [28]) over the first gate dielectric layer (152, [28]),
wherein a portion of the first gate dielectric layer (152, [28]) is disposed along a sidewall of the region isolation feature (120/199 between 170A and 170B, [28], figures).
Regarding claim 3, Guler in view of Chen discloses the semiconductor structure of claim 2 as described above.
Guler further discloses, in at least figures 1A-1B and related text, the first gate cut feature (121B, [28]) is in direct contact with the first gate electrode layer (150, [28]).
Regarding claim 4, Guler in view of Chen discloses the semiconductor structure of claim 1 as described above.
Chen further teaches, in at least figures 15A-15C and related text, a bottom surface of the region isolation feature (50/66, [41]) is lower than a bottom surface of the first gate cut feature (leftmost 50, [41], figures), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Regarding claim 5, Guler in view of Chen discloses the semiconductor structure of claim 1 as described above.
Chen further teaches, in at least figures 15A-15C and related text, the second gate cut feature (rightmost 50, [41], figures) continuously taper from a top surface of the second gate structure (right 42/43/44, [29], figures) toward the isolation structure (26, [16]) (figures), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Regarding claim 6, Guler in view of Chen discloses the semiconductor structure of claim 1 as described above.
Chen further teaches, in at least figures 15A-15C and related text, the region isolation feature (50/66, [41]) comprises a lower portion and an upper portion over the lower portion, wherein a width of the region isolation feature (50/66, [41]) along the direction (horizontal direction, figures) undergoes a step change between the lower portion and the upper portion (figures), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Regarding claim 7, Guler in view of Chen discloses the semiconductor structure of claim 6 as described above.
Chen further teaches, in at least figures 15A-15C and related text, the lower portion (lower portion of 50/66, [41], figures) tapers downward (figures), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Regarding claim 8, Guler in view of Chen discloses the semiconductor structure of claim 6 as described above.
Chen further teaches, in at least figures 15A-15C and related text, the upper portion (upper portion of 50/66, [41], figures) tapers downward (figures), for the purpose of providing devices formed with the fins having increased performance by retaining more stress ([43]).
Allowable Subject Matter
Claims 9-16 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action because the prior art of record, US 2021/0183855 in view of US 2019/0131297, neither anticipates nor render obvious the limitations of the base claims 9 that recite "after the forming of the region isolation feature, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first fin-shaped structure and a second metal gate structure over the third fin-shaped structure" in combination with other elements of the base claims 9.
Claims 17-20 are allowed because the prior art of record, US 2021/0183855 in view of US 2019/0131297, neither anticipates nor render obvious the limitations of the base claims 17 that recite "after the forming of the region isolation feature, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first active region and a second metal gate structure over the third active region" in combination with other elements of the base claims 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811