Prosecution Insights
Last updated: April 19, 2026
Application No. 18/518,081

Metal Contact Structure and Method of Forming the Same in a Semiconductor Device

Non-Final OA §112§DP
Filed
Nov 22, 2023
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
80%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
358 granted / 546 resolved
-2.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
40 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§112 §DP
Attorney’s Docket Number: TSMP20140239US02 Filing Date: 11/22/2023 Claimed Priority Dates: 11/2/2020 (US 17/086,754) 4/25/2024 (US 14/262,467) Inventors: Lin et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment in paper no. 5 filed 2/26/2001. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis, i.e., changing from AIA to pre-AIA , for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 9-14 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Claim 9 recites the steps of depositing a first metal layer comprising Co and a second metal layer comprising Ti. The claim further recites annealing to form an amorphous layer between the first and second metal layer comprising Ni-Ta. The specification, as originally filed, fails to support these limitations in the claim. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-11 of Lin (US 11,854,874). Although the claims at issue are not identical, they are not patentably distinct from each other as set forth below. Regarding claim 15, Lin anticipates the limitations recited in the claim including a method comprising: Forming a conductive contact extending through a dielectric layer to a top surface of a semiconductor substrate (claim 7/ll.1-4), the contact comprising: A first metal layer comprising cobalt (claim 7/ll.5-7) A second metal layer comprising titanium (claim 7/ll.8-9), and A third metal layer comprising ruthenium (claim 7/ll.10-11), and Performing a thermal treatment on the contact to form a cobalt silicide in the substrate and a Co-Ti layer between the first and second metal layers (claim 7/ll.15-20). Regarding claim 16, Lin (claim 7/ll.10-14) anticipates the limitations recited in the claim. Regarding claim 17, Lin (claim 9) anticipates the limitations recited in the claim. Regarding claims 18 and 19, Lin (claim 11) anticipates the limitations recited in the claims. Regarding claim 20, Lin (claim 8) anticipates the limitations recited in the claim. Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of Lin in view of Boemmels (US 2009/0035936) and Chiang (US 5739579). Regarding claim 1, Lin anticipates most of the limitations recited in the claims including a method of forming a semiconductor device comprising: Forming an opening in a dielectric layer over a substrate (claim 13/ll.1-4) Sequentially forming first and second metal layer in the opening (claim 13/ll.3-6), and Performing an annealing process to form an amorphous layer between the first and second metals comprising Ni-Ta and a silicide layer between the first metal and the substrate (claim 13/ll.11-15) The patented claims, however, differently recite “an opening defined in a dielectric layer” instead of “patterning an opening in a dielectric layer” as recited in the application claims. Lin teaches that the dielectric opening is an exemplary single damascene opening. Boemmels teaches that in a typical and well-established single damascene process, a dielectric layer is deposited first and subsequently patterned. See, e.g., Boemmels: par.0008, 0010, 0011/ll.1-3, 0012/ll.1-9, 0059/ll.8-10. Chiang further teaches that a common method of forming interconnect contacts, like the one in Lin, includes the step of forming a patterned dielectric layer having openings to underlying layers (see, e.g., col.1/ll.30-32). Boemmels and Chiang both demonstrate that patterning dielectric layers to form openings is a routine and well-established method in single damascene manufacturing. Patterning is the conventional method by which openings are defined in a dielectric prior to metallization. Because Lin already claims forming an opening in a dielectric, incorporating the conventional patterning step taught by Boemmels and Chiang would merely involve applying a known and predictable technique to achieve the same result, i.e., defining an opening in a dielectric. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). Accordingly, it would have been obvious at the time of filing the invention to a person having ordinary skill in the art to modify Lin’s method to explicitly include the step of patterning the dielectric to form an opening, as taught by Boemmels and Chiang, since patterning was a well-established and conventional semiconductor fabrication technique that would have been routinely employed by the skilled artisan in a manner compatible with conventional processes and with predictable results. Regarding claim 2, Lin (claim 14) anticipates the limitations recited in the claim. Regarding claim 3, Lin (claim 15) anticipates the limitations recited in the claim. Regarding claims 4 and 6, Lin (claim 13) anticipates the limitations recited in the claims. Regarding claim 5, Lin (claim 16) anticipates the limitations recited in the claim. Regarding claim 7, Lin (claim 17) anticipates the limitations recited in the claim. Regarding claim 8, Lin (claim 18) teaches annealing after planarizing the first and second metal layers. Boemmels (see, e.g., 4b and 3e) and Chiang (see, e.g., fig. 7) both show planarizing the first and second metal layers and the dielectric layer. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp March 5, 2026
Read full office action

Prosecution Timeline

Nov 22, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §112, §DP (current)

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
80%
With Interview (+14.8%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allow rate.

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