Prosecution Insights
Last updated: October 22, 2026
Application No. 18/518,151

SRAM ARCHITECTURE FOR CONVOLUTIONAL NEURAL NETWORK APPLICATION

Final Rejection §112
Filed
Nov 22, 2023
Priority
Aug 25, 2020 — continuation of 11/853,880
Examiner
SIDDIQUE, MUSHFIQUE
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
751 granted / 838 resolved
+21.6% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
19 currently pending
Career history
862
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
43.8%
+3.8% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§112
DETAILED ACTION This Final action is responsive to communications: 08/19/2026. Claims 1, 9, 12, 14, 15, 17, and 20 have been amended. Claims 8 and 16 have been canceled. Claims 21 and 22 are new. Claims 1-7, 9-15, 17-22 are pending. Claims 1, 9, and 17 are independent. Examiner Notes A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Domestic Priority 4. See ADS for domestic CON priority details. Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard. Claim Rejections - 35 USC § 112 5. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 6. Claims 1, 9, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements, steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For claims 1, 9, and 17 omitted elements are described in bold in association with each limitation: Claim 1. A convolutional neural network (CNN) comprises: a first cell array including a plurality of first memory cells, wherein each of the plurality of first memory cells is configured to multiply a weight bit and an input bit and comprises a corresponding one of a plurality of first analog devices, and (Missing elements are construction of “first memory cell”, “first analog devices”, description of associated segments. See Fig. 5A: 203A memory cell where 502 is the SRAM weight, 505 is the capacitor, M1, M2 are transistors. See also, Fig. 2A-Fig. 2E: 209 which can be part of analog device or, part of cell component. Due to lack of description and missing elements “first memory cell”, “first analog devices” cannot be recognized. Further, boundary of different components cannot be recognized) wherein the plurality of first analog devices are selectively enabled based on the respective weight bits and input bits; and a second cell array comprising a plurality of second memory cells, wherein each of the plurality of second memory cells comprises a corresponding number of second analog devices that are enabled by a corresponding reference bit (Missing elements are construction of “second memory cell”, “second analog devices”, description of associated segments. See above. Further, boundary of different components cannot be recognized); and an offset cell to compensate for mismatch of a first property of the plurality of first analog devices and a second property of the second analog devices. Claim 9. A convolutional neural network (CNN) comprises: a first cell array including a plurality of first memory cells, wherein each of the plurality of first memory cells is configured to multiply a weight bit and an input bit and comprises a corresponding one of a plurality of first analog devices, and (Missing elements are construction of “first memory cell”, “first analog devices”, description of associated segments. See Fig. 5A: 203A memory cell where 502 is the SRAM weight, 505 is the capacitor, M1, M2 are transistors. See also, Fig. 2A-Fig. 2E: 209 which can be part of analog device or, part of cell component. Due to lack of description and missing elements “first memory cell”, “first analog devices” cannot be recognized. Further, boundary of different components cannot be recognized) wherein the plurality of first analog devices are selectively enabled based on the respective weight bits and input bits; a second cell array comprising a plurality of second memory cells, wherein each of the plurality of second memory cells comprises a corresponding number of second analog devices that are enabled by a corresponding reference bit; and (Missing elements are construction of “second memory cell”, “second analog devices”, description of associated segments. See above. Further, boundary of different components cannot be recognized); an offset cell to compensate for mismatch of a first property of the plurality of first analog devices and a second property of the second analog devices, a controller configured to: compare a first signal associated with the plurality of first analog devices with a second signal associated with at least one of the plurality of second analog devices; and based on the comparison, determine whether at least one of the first analog devices is enabled. (“enabled” state of the first analog device is not understood due to missing description). Claim 17. A convolutional neural network (CNN) comprises: a first cell array including a plurality of first memory cells, wherein each of the plurality of first memory cells is configured to multiply a weight bit and an input bit and comprises a corresponding one of a plurality of first capacitive elements, and wherein the plurality of first capacitive elements are selectively enabled based on the respective weight bits and input bits; (Missing elements are construction of “first memory cell”, “first capacitive elements”, description of associated segments. See Fig. 5A: 203A memory cell where 502 is the SRAM weight, 505 is the capacitor, M1, M2 are transistors. See also, Fig. 2A-Fig. 2E: 209 which can be part of capacitive elements or, part of cell component. Due to lack of description and missing elements “first memory cell”, “first capacitive elements” cannot be recognized. Further, boundary of different components cannot be recognized) a second cell array comprising a plurality of second memory cells, wherein each of the plurality of second memory cells comprises a corresponding number of second capacitive elements that are enabled by a corresponding reference bit; and (Missing elements are construction of “second memory cell”, “second capacitive elements”, description of associated segments. See Fig. 5A: 203A memory cell where 502 is the SRAM weight, 505 is the capacitor, M1, M2 are transistors. See also, Fig. 2A-Fig. 2E: 209 which can be part of capacitive elements or, part of cell component. Due to lack of description and missing elements “second memory cell”, “second capacitive elements” cannot be recognized. Further, boundary of different components cannot be recognized; an offset cell to compensate for mismatch of a first property of the plurality of first capacitive elements and a second property of the second capacitive elements; a controller configured to: compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one of the plurality of second capacitive elements; and based on the comparison, determine whether at least one of the first capacitive elements is enabled. (“enabled” state of the capacitive elements is not understood due to missing description). 7. All dependent claims inclusive of claims 1-7, 9-15, 17-22 are rejected under this category. Response to Arguments Based on amendments of claims 12, 14, 15, and 20 and persuasive arguments (see page 7 of Remarks filed 08/19/26), previous 112b rejection of claims (previous OA section 7a) have been withdrawn. Applicant’s arguments, see Remarks filed 08/19/26 (pages 8-10), with respect to (35 U.S.C. § 102(a)(1) anticipation rejection over Patent Publication No. 2021/0343343 "Teague") have been fully considered and are found persuasive. Therefore, the prior art rejections are being withdrawn. 1. Applicant argues that the 35 U.S.C. § 112(b) rejection of claims 1, 9, and 17 for being incomplete for omitting essential elements are not proper because “…the present Specification does not characterize any single structural arrangement of the claimed memory cells or analog devices as essential or necessary to practice the invention….” Applicant’s argument is not persuasive because spec describe these as integral part of the device. Spec do not describe these features as "preferred," "optional," or "illustrative". See Fig. 5A: 203A memory cell where 502 is the SRAM weight, 505 is the capacitor, M1, M2 are transistors. See also, Fig. 2A-Fig. 2E: 209 which can be part of analog device or, part of cell component. Due to lack of description and missing elements “first memory cell”, “first analog devices” cannot be recognized. Further, boundary of different components cannot be recognized. See also Fig. 6A-Fig. 6B and associated disclosure in para [0060]-para [0062]. Even though the Specification describes the analog devices in exemplary terms and discloses multiple alternative memory-cell embodiments, the claim language needs to capture all essential components so that the overall device and function can be understood. Omitting these components (with additional distinguishing descriptions) can create an incomplete device or method where the claimed subject matter fails to operate or achieve the stated purpose (e.g., claiming a car but omitting the engine). 2. Applicant argues that the 35 U.S.C. § 112(b) rejection of claims 1, 9, and 17 for being incomplete for omitting essential elements are not proper because Examiner was able to make rejection using element to element matching. Applicant’s argument is not persuasive because art rejection is independent. Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. Therefore, the 112b rejection for omitting essential elements is being maintained. Allowable Subject Matter Claims 1, 9, and 17 are being rejected under 112b rejection (see section 7, 8 above), but would be allowable if rewritten to over-come the 112b rejections. Regarding Claims 1, 9, and 17 (and associated dependent claims inclusive of Claims 1-7, 9-15, 17-22 ) , the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims. Prior Art Not Relied Upon The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: HWANG (US 2021/0334633 A1): Fig. 1-Fig. 14 disclosure applicable for all claims. PASSOTTI (US 2022/0068400 A1): Fig. 1-Fig. 5 disclosure applicable for all claims. Dhori (US 2017/0301396 A1): Fig. 1-Fig. 4 disclosure applicable for all claims. Song (US 2021/0166110 A1): Fig. 1-Fig. 9 disclosure applicable for all claims. It is suggested that applicant consider all prior arts made of record. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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Prosecution Timeline

Nov 22, 2023
Application Filed
May 26, 2026
Non-Final Rejection mailed — §112
Aug 19, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.1%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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