Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 11/22/23. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 11/22/23 has been received and are being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. §102(a)(1)(2) as being unpatentable over Peng (US 20210343650 A1).
Regarding claim 1, Peng discloses an electronic device, comprising: a first module having a first electronic component (see fig 1cb disclosing first and second D1-3, see para [0178] disclosing encapsulant DL); a second module at least partially overlapped with the first module and having an encapsulant (see D2 partially overlapping D1); and a first power path (see V/VT)penetrating through the encapsulant (see fig 1cb, disclosing V is formed through DL) and providing a first power signal to a backside surface of the first electronic component (see fig 1cb disclosing backside power).
Regarding claim 2, Peng discloses the electronic device of claim 1, wherein the second module further comprises a second electronic component covered by the encapsulant, and the first power path is outside of the second electronic component (see D1/D2, where DL encapsulates both and V is formed outside D1/D2).
Regarding claim 3, Peng discloses the electronic device of claim 2, wherein the second electronic component and the first power path are non-overlapped (see V to the right are non-overlapped with devices).
Regarding claim 4, Peng discloses the electronic device of claim 2, further comprising: a second power path at least partially within the first module and configured to provide a second power signal to a backside surface of the second electronic component (see V on the left side of D1 providing power to D2).
Regarding claim 5, Peng discloses the electronic device of claim 4, wherein the first electronic component and the second power path are non-overlapped (see D2 and V are non-overlapped).
Regarding claim 6, Peng discloses the electronic device of claim 4, wherein the second power path is outside of the first electronic component (see V on the right is outside of D1 and D2).
Regarding claim 7, Peng discloses the electronic device of claim 4, wherein the first module further comprises a first carrier over which the first electronic component is disposed (see CPD1), and wherein the first carrier serves as a part of the first power path and a part of the second power path (see CPS1 is attached to CPD4/V).
Regarding claim 8, Peng discloses the electronic device of claim 7, wherein the second module further comprises a second carrier over which the encapsulant is disposed, wherein the second carrier serves as a part of the first power path (see CPD2 is attached to CPD4?V).
Regarding claim 9, Peng discloses the electronic device of claim 1, wherein the first electronic component has a power circuit adjacent to the backside surface and configured to receive the first power signal through the first power path (see CPD1,2,4 receiving power from V and distributing to D1/D2).
Regarding claim 10, Peng discloses the electronic device of claim 1, wherein the first module further comprises an encapsulant spaced apart from the encapsulant of the second module (see surrounding DL), and the electronic device further comprises: a second power path penetrating through the encapsulant of the first module and provide a second power signal to a backside surface of a second electronic component of the second module (see V on the right penetrating through backside surface planes).
Regarding claim 11, Peng discloses the electronic device of claim 10, wherein a length of the second power path is greater than a length of the first power path (See V on the right is longer than V on the left).
Regarding claim 12, Peng discloses the electronic device of claim 1, wherein the first module further comprises a power regulating device disposed over the backside surface of the first electronic component (see para [0025] disclosing any one of the D1-3 are regulators).
Regarding claim 13, Peng discloses the electronic device of claim 12, wherein the second module further comprises a conductive element partially exposed from the encapsulant and electrically connected with the power regulating device (see V penetrates through CPD4 into VT).
Regarding claim 14, Peng disclosing the electronic device of claim 1, wherein the first module further comprises an encapsulant covering the encapsulant of the second module ( (see DL covering D1/D2)).
Regarding claim 15, Peng discloses an electronic device, comprising: a first electronic component having a backside surface (see fig 1cb D2 has backside); a second electronic component overlapped with the first electronic component (see D1 overlaps D2)and exposing a portion of the backside surface (see D2 is exposed); and a first power path outside of the second electronic component and crossing a lateral surface of the second electronic component (see left side of D1 where V is underneath D2), wherein the first power path provides a first power signal to the backside surface of the first electronic component (see para [0142] disclosing D2 electrically supplied by V).
Regarding claim 16, Peng discloses the electronic device of claim 15, wherein a backside surface of the second electronic component faces the backside surface of the first electronic component (see D1 faces D2, fig 1cb).
Regarding claim 17, Peng discloses the electronic device of claim 16, wherein a second power path outside of the first electronic component and crossing a lateral surface of the first electronic component (see V crosses both D1 and D2)and provide a second power signal to the backside surface of the second electronic component (see V and CPD1/2/4 providing power to D1 and D2 backside).
Regarding claim 18, Peng, at least at fig 1cb discloses an electronic device, comprising: a first electronic component D2; a first encapsulant encapsulating the first electronic component DL; a first conductive element adjacent to the first electronic component and encapsulated by the first encapsulant (V); and a second electronic component spaced apart from the first encapsulant and covering the conductive element (D1), wherein the second electronic component is configured to receive a power from the first conductive element (see CPD1,2,4 distributing power from V and D1/d2).
Regarding claim 19, Peng discloses the electronic device of claim 18, further comprising: a second encapsulant encapsulating the second electronic component and spaced apart from the first encapsulant (see fig 1cb disclosing multiple DL); and an electrical contact within a gap between the first encapsulant and the second encapsulant and electrically connecting the first conductive element and the second electronic component (see position of V interstitial to DL).
Regarding claim 20, Peng discloses the electronic device of claim 18, further comprising: a second conductive element disposed over the first electronic component (D1 over D2) and electrically connecting the first electronic component and the second electronic component (see CPD1/2/4), wherein the first encapsulant has an upper surface substantially coplanar with an upper surface of the first conductive element and the second conductive element (see DL having coplanar surfaces).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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