DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
Non claim to an application for domestic benefit.
Foreign Priority
No claim to an application for foreign priority.
Two Information Disclosure Statements
The two information disclosure statements submitted on 04/01/2025 and 08/28/2025 were filed before first Office action. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the two information disclosure statements have been considered.
Claim Objections
Claim 3 is objected to because of the following minor typographical informalities: it appears that this step may form the lower spacer not the upper spacer. Appropriate correction is required.
Claim 17 is objected to because of the following minor typographical informalities: recites “ling” instead of “lining”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6 and 8-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0262804 A1 to Fan.
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Regarding independent claim 1, Fan teaches a method for preparing an air gap between bit line structure and capacitor contact (see title & as defined below), comprising:
defining a plurality of active regions 105 by forming a device isolation layer 103 in a substrate 101 (see Figures 2-3);
forming a semiconductor layer 115 and a metal layer 117 on the active regions 105 (see Figures 6-7);
forming a first mask 121 intersecting the active regions 105 on the metal layer 117 (see Figures 6-7);
etching the semiconductor layer 115 and the metal layer 117 using the first mask 121 as etch mask 121 to form a plurality of bit line structures 119 (see Figures 8-9);
forming a plurality of lower spacer structures 137/131/133/135 with an energy removable material 133 on sidewalls of the plurality of bit line structures 119 (see Figures 10-11);
forming a second mask (i.e., may be considered parts of 121) over the metal layer 119;
forming a plurality of upper spacer structures 149 over the plurality of lower spacer structures 137/131/133/135 (see Figures 14-15);
forming a dielectric layer 151 surrounding the upper spacer structures 149 and covering the metal layer 119 (see Figures 16-17);
forming a plurality of capacitor contacts 143 including a barrier layer (see paragraph 0041: it appears that a barrier layer may be directly touching 142 therefore the barrier layer may be considered part of the claimed capacitor contacts) and a conductor layer 143;
performing a thermal treating process (see paragraphs 0066-0067) to transform the plurality of first spacer structures (see Figure 18) into a plurality of air gap structures 156 (Figures 17-18).
Regarding claim 3, Fan teaches conformally depositing the energy removable material overlying the first mask and the metal layer; and etching the energy removable material by an anisotropic etching process (as stated in paragraph 0060, “Some processes used to form the middle spacers 133 and the outer spacers 135 are similar to, or the same as those used to form the inner spacers 131, and details thereof are not repeated herein.” Therefore as covered in paragraph 0060, 131 is conformally deposited and anisotropically etched).
Regarding claim 4, Fan teaches wherein forming the dielectric layer 151 surrounding the upper spacer structures 149 and covering the metal layer 119 comprising: depositing a dielectric material 151 overlying and covering the upper spacer structures 149 and the metal layer 119; and planarizing (i.e., as stated in paragraph 0066: “Some materials and processes used to form the second dielectric layer 151 are similar to, or the same as those used to form the first dielectric layer 141 (see FIGS. 10 and 11), and details thereof are not repeated herein.” A stated in paragraph 0061; there is deposition and planarization) the dielectric material 151 until the first mask 121 is exposed (i.e., necessarily so in order to form 153).
Regarding claim 6, Fan teaches wherein the conductive layer 143 is formed by a deposition process (see paragraph 0062).
Regarding claim 8, Fan teaches wherein performing a thermal treating process (paragraphs 0067-0068) forms the air gap 156 enclosed by a liner 131/135.
Regarding independent claim 9, Fan teaches a method for manufacturing a semiconductor device (see title and drawings), comprising:
forming a first source/drain region (see paragraph 0039; 105a) and a second source/drain region (see paragraph 0039: 105b) in a semiconductor substrate 101;
forming a bit line structure 119 over and electrically connected to the first source/drain region 105a (see Figure 9);
forming a capacitor contact 143 over and electrically connected to the second source/drain region 105b (see Figure 13);
forming a first spacer structure 137 between the bit line structure 119 and the capacitor contact 143, wherein the first spacer structure 137 comprises an air gap 156 (see Figure 18); and
forming a second spacer structure 149 over the first spacer structure 137, wherein the air gap 156 is covered by the second spacer structure 149.
Regarding claim 10, Fan teaches forming a semiconductor layer 115 over the semiconductor substrate 101; forming a metal layer 117 over the semiconductor layer 115; and performing an etching process (see Figure 7 to Figure 9) on the semiconductor layer 115 and the metal layer 117.
Regarding claim 11, Fan teaches further forming a patterned mask 121 over the bit line structure 119.
Regarding claim 12, Fan teaches further forming a dielectric layer 151 over the second spacer structures 149 and the patterned mask 121.
Regarding claim 13, Fan teaches further forming a conductive pad 153 covering the second spacer structure 149 and covering portions of the patterned mask 121.
Regarding claim 14, Fan teaches wherein the conductive pad 153 is disposed over and electrically connected to the capacitor contact 143.
Regarding claim 15, Fan teaches further performing a thermal treating process (paragraphs 0066-0067) to transform the first spacer structure 137 into an air gap structure 156, wherein the air gap structure 156 including the air gap enclosed by a liner (see Figure 18; liner may be considered 131/135).
Regarding claim 16, Fan teaches wherein the air gap structure 137/156 and the air gap 156 extend into the semiconductor substrate 101 (see Figure 18).
Regarding claim 17, Fan teaches wherein the capacitor contact 143 comprises a barrier layer (as stated in paragraph 0041 there appears to be a barrier layer directly touching the capacitor contacts and therefore may be considered part of the barrier layer) and a conductive layer 143 the barrier layer
Allowable Subject Matter
Claims 2, 5, 7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 2, depositing the energy removable material over the metal layer; and planarizing the energy removable material until the metal layer is exposed.
Claim 5 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 5, wherein the barrier layer is formed by an anisotropic deposition process.
Claim 7 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 7, wherein the barrier layer has a first thickness on the sidewall of the corresponding conductive layer and a second thickness under the bottom surface of the corresponding conductive layer.
Claim 18 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 18, wherein the barrier layer has a first thickness on the sidewall of the corresponding conductive layer and a second thickness under the bottom surface of the corresponding conductive layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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04 April 2024
/John P. Dulka/Primary Examiner, Art Unit 2817
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