Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention II in the reply filed on 04/16/2026 is acknowledged. The traversal is on the ground(s) that both claims 8 and 31 require the technical features "a width of the inner spacer limited by a canal which is alone a longitudinal direction of the gate structure, and the inner spacer at least covers sidewalls of the fin body" and the currently amended claim 21 of the present invention is amended to depend on the currently amended claim 8 of the present invention. Examiner agrees that claims 21-28 are no longer restricted in view of the amendment however this is not found persuasive because the restriction is not under unity of invention but standard US practice so that the presence of a shared technical feature would not necessarily mean inventions II and IV are not restrictable. Although claim 31 has been amended the method of claim 31 could still be used to form a different device than that claimed in claim 8 for example one wherein the gate is confined to the fin and not covering a first portion of the shallow trench isolation region as required by claim 8 so that groups II and IV are still restrictable and the same search burden as discussed in the restriction mailed 02/24/2026 would still apply examiner noted that if claim 31 is amended to require all the limitations of an ultimately allowable claim it may be considered for rejoinder.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-7 and 31-39 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/16/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the first conductive region”, “the second conductive region” and “the inner spacer at least covers sidewalls of the fin body” must be shown or the feature(s) canceled from the claim(s). Examiner notes that while structures such as 1702, 1704, 1706, 1708 and 1710 or some combination thereof could correspond to the claimed first and second conductive region however it is unclear which does. Examiner notes that the fin body is removed from under the inner spacer in Fig. 16 so that it does not cover sidewalls of the fin body in the final device No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 12 and 25 objected to because of the following informalities: “that of other portion of the shallow trench isolation region” should be --that of another portion of the shallow trench isolation region--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9, 13-18, 21-22, and 26-28 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et. Al. (US 20150035046 A1 hereinafter Kim).
Regarding claim 8, Kim teaches in Figs. 1A-1C and 21A with associated text a semiconductor transistor comprising: a semiconductor substrate (100 and FP1a) with an original surface (for example upper surface) (Figs, 1A-1C); an active region (FP1a and S/D) formed based on the semiconductor substrate, the active region having a fin structure FP1a (Fig. 1A-1C, [0075]); a shallow trench isolation region (DIP) surrounding the active region (Fig. 1A-1C, [0084]); a gate structure (150-160) of the semiconductor transistor crossing over the fin structure and covering a first portion of the shallow trench isolation region (Fig. 1A-1C, [0084]); a first conductive region and a second conductive region (S/D on left and right respectively) of the semiconductor transistor located within the active region (Fig. 1A-1C, [0090]); a canal along (space between gate and S/D filled by spacers (135 and 120)) a longitudinal direction of the gate structure (Fig. 1A-1C); and an inner spacer (135 and 120) filled in the canal and contacted to a sidewall of the gate structure (Fig. 1A-1C, [0089]), wherein a width of the inner spacer limited by the canal (Fig. 1C); wherein the fin structure comprises a fin body (CPa of Fig. 1A-1C or C2A of Fig. 21A) and a fin base ((BP and IPa) of Figs. 1A-1C or (BP IPa and C1a) of Fig. 21A) (Fig. 1A-1C and 21A, [0077]), the fin body is covered by the gate structure, and the inner spacer at least covers sidewalls of the fin body (Fig. 1A-1C).
Regarding claims 13 and 21, Kim teaches the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, the perpendicular profile of the fin structure provides a first step-like transition or non-gradual transition (Fig. 1B pr Fig. 21A).
Regarding claims 9 and 22, Kim teaches the inner spacer further covers portion sidewalls of the fin base (here the fin base is interpreted to be (BP IPa and C1a) of Fig. 21a so that the gate and spacer covers portion sidewalls C1a) Fig. 21A).
Regarding claims 14 and 26, Kim teaches the first step-like transition or non-gradual transition is between the fin body and the fin base (Fig. 1B pr Fig. 21A).
Regarding claims 15 and 27, Kim teaches the fin structure has a lateral profile along a direction substantially parallel to the original surface (direction along the width of the fin), wherein the lateral profile of the fin structure provides a second step-like transition (transition between C1a and IPa examiner notes that any of the steps can be considered a step in the width or a step in the height direction) or non-gradual transition (Fig. 21A).
Regarding claims 16, Kim teaches the second step-like transition or non-gradual transition is between the gate structure and the first conductive region (the portion under the spacer is between the gate and the first conductive region).
Regarding claims 17, Kim teaches the lateral profile of the fin structure further provides a third step-like transition (transition between IPa and BP) or non-gradual transition (Fig. 21A) which is between the gate structure and the second conductive region (the portion under the spacer is between the gate and the first conductive region).
Regarding claims 18 and 28, Kim teaches the first conductive region and/or the second conductive region is limited by the shallow trench isolation region (110a limits the bottom part of S/D 3Fig. 1A).
Claim(s) 8, 11, 13, 19-20, 21, 24 and 29-30 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Zhu et. Al. (US 20090008705 A1 hereinafter Zhu).
Regarding claim 8, Zhu teaches in Figs. 14A-14D with associated text a semiconductor transistor comprising: a semiconductor substrate (10, 20, 30, 32, 41 and 72) with an original surface (for example upper surface) (Figs, 14A-14D); an active region (32, 41 and 72) formed based on the semiconductor substrate (Fig. 14B, [0066]), the active region having a fin structure (32 and 41) (Fig. 14A-14D, [0066]); a shallow trench isolation region 62 surrounding the active region (Fig. 14A-14D, [0056]); a gate structure (70 and 56) of the semiconductor transistor crossing over the fin structure and covering a first portion of the shallow trench isolation region (Fig. 14C, [0061]); a first conductive region and a second conductive region (72 on the left and right respectively) of the semiconductor transistor located within the active region (Fig. 14B, [0056]); a canal along (space between gate and dielectric 100 filled by spacers (80 and 88) a longitudinal direction of the gate structure (Fig. 14B and 14D); and an inner spacer (80 and 88) filled in the canal and contacted to a sidewall of the gate structure (Fig. 14B and 14D, [0060] and [0067]), wherein a width of the inner spacer limited by the canal (Fig. 14B and 14D); wherein the fin structure comprises a fin body 41 and a fin base 32 (Fig. 14A-14D and 21A, [0077]), the fin body is covered by the gate structure (Fig. 14C), and the inner spacer at least covers sidewalls of the fin body (Fig. 14B-14D).
Regarding claims 13 and 21, Zhu teaches the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, the perpendicular profile of the fin structure provides a first step-like transition (transition in 32at 54 Fig. 14C) or non-gradual transition (Fig. 14C).
Regarding claims 11 and 24, Zhu teaches at least two sides of the first conductive region or the second conductive region are contacted to a metal-containing region 92 (Fig. 14B, [0072]).
Regarding claims 19 and 29, Zhu teaches a bottom of the gate structure over the first portion of the shallow trench isolation region is lower than that of the first conductive region and/or the second conductive region (gate 70 extends down to contact STI 62 Fig. 14C which is lower than bottom of 72 14B).
Regarding claims 20 and 30, Zhu teaches the first conductive region and the second conductive region are independent from the fin structure and not over the shallow trench isolation region (Fig. 14B and 14C).
Claim(s) 8, 12-13, 21 and 25 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Xie et. Al. (US 20150371892 A1 hereinafter Xie).
Regarding claim 8, Xie teaches in Fig. 2L with associated text a semiconductor transistor comprising: a semiconductor substrate (102, 106A, 106, 122 and 110) with an original surface (for example upper surface) (Fig, 2L); an active region (106A, 106 and 122) formed based on the semiconductor substrate, the active region having a fin structure (106A, 106 and 122) (Fig. 2L, [0026] and [0031]); a shallow trench isolation region 110 surrounding the active region (Fig. 2L, [0029]); a gate structure (130A, 130B) of the semiconductor transistor crossing over the fin structure and covering a first portion of the shallow trench isolation region (Fig. 2L, [0035]); a first conductive region and a second conductive region (122 on left and right respectively) of the semiconductor transistor located within the active region (Fig. 2L, [0031]); a canal along (space between gate and 122/126 filled by spacers 118) a longitudinal direction of the gate structure (Fig. 2L); and an inner spacer 118 filled in the canal and contacted to a sidewall of the gate structure (Fig. 2L, [0030]), wherein a width of the inner spacer limited by the canal (Fig. 2L); wherein the fin structure comprises a fin body 106 and a fin base 106A (Fig. 2L, [0026]), the fin body is covered by the gate structure (Fig. 2L), and the inner spacer at least covers sidewalls of the fin body (Fig. 2L).
Regarding claims 13 and 21, Xie teaches the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, the perpendicular profile of the fin structure provides a first step-like transition or non-gradual transition (transition between 106A and 106 for example) (Fig. 2L).
Regarding claims 12 and 25, Xie teaches a top surface of the first portion of the shallow trench isolation region covered by the gate structure (Fig. 2L view Y-Y) is lower than that of other portion of the shallow trench isolation region not covered by the gate structure (Fig. 2L view Z-Z, [0034]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 8 and 21 and further in view of Luo et. Al. (US 20120025328 A1 hereinafter Luo).
Regarding claims 10 and 23, Kim teaches the semiconductor transistor of claims 8 and 21. .
Kim does not specify the inner spacer is a composite spacer comprises an oxide sub-spacer and a SiCOH sub-spacer surrounding sidewalls and a top surface of the oxide sub-spacer.
Luo discloses in Fig. 5 with associated text an inner spacer (1006”, 1007 and 1008) is a composite spacer comprises an oxide sub-spacer 1006” (Fig. 6, [0031]) and a SiCOH sub-spacer 1008 surrounding sidewalls and a top surface of the oxide sub-spacer (Fig. 5, [0034])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use spacers similar to those of Luo in the device of Kim because according to Luo in such an arrangement, La element in the first spacer can diffuse into the gate dielectric layer, facilitating the adjustment for Vt of the device, and the first spacers are relatively low so as not to significantly increase the parasitic capacitance for the gate [0038] the introduction of a material such as La into the gate dielectric layer material will effectively lower the threshold voltage (Vt) of a transistor, which helps to improve the device performance [0004].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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