Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 5/7/2026. Applicant has elected Group II, corresponding to claims 1-10. Invention Group I, corresponding to claims 11-20, is withdrawn from further consideration.
Specification
The specification submitted 11/24/2023 has been accepted by the examiner.
Drawings
The drawings submitted up to this point including the 5/7/2026 replacement drawing, have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Altstatter (US # 20230307538).
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Regarding Claim 1, Alstatter-538 teaches a semiconductor device (Figs. 1 and corresponding text), comprising:
a substrate (11), having a first surface (12) and a second surface (13);
a gate pad (21) and a source pad (22), laterally separated from each other, and both disposed on the first surface of the substrate (shown with gap 38 between);
a drain region (23), disposed on the second surface of the substrate (shown);
a first trench (16), disposed in the substrate and directly below the gate pad (shown) for at least a subset under 21);
a conductive portion (17), filling up the first trench (see Fig. 1B);
a dielectric liner (27), disposed in the first trench and surrounding the conductive portion (shown);
a first doped region (portions of 24 nearer to trenches 16), located on two sides of the first trench (shown);
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a second trench (30), disposed in the substrate and directly below the source pad (at least a subset of the trenches 30 are directly below feature 22);
a gate electrode (19), filling up the second trench (shown);
a gate dielectric layer (31), disposed in the second trench and surrounding the gate electrode (shown); and
a source region (26), located on two sides of the second trench (shown), wherein the first doped region (18) and the source region have the same conductivity type ([0064, 91] teaches first-conductivity type).
Regarding Claim 2, Alstatter-538 teaches the semiconductor device of claim 1, wherein the dielectric liner (27) comprises a first portion located on sidewalls (28) of the first trench and a second portion located on a bottom surface (29) of the first trench (shown with a bottom portion that has a larger dimension, very similar to the applicant’s T1 > T2; see also [0065]), the second portion has a thickness greater than a thickness of the first portion, the gate dielectric layer (31) comprises a third portion located on sidewalls of the second trench and a fourth portion located on a bottom surface of the second trench, and the fourth portion has a thickness greater than a thickness of the third portion (shown with a bottom portion that has a larger dimension, very similar to the applicant’s T1 > T2; see also [0067]).
Regarding Claim 3, Alstatter-538 teaches the semiconductor device of claim 1, wherein the gate electrode (19) and the conductive portion (17) are both electrically coupled to the gate pad (21), and the first doped region (24) and the source region (26) are both electrically coupled to the source pad (22; see [0070, 71]).
Allowable Subject Matter
Claims 4-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including the semiconductor device of claim 1, wherein the substrate comprises an epitaxial layer located on the drain region, a well region is disposed in the epitaxial layer, the well region is laterally extended from being directly below the gate pad to be directly below the source pad, the first doped region and the source region both have a first conductivity type, the well region has a second conductivity type, the drain region and the epitaxial layer both have the first conductivity type, and the first doped region and the source region are both disposed in the well region.
Claims 5-10 are dependent upon claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached on normally working Monday-Friday between 9 am and 6 pm Pacific Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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