Prosecution Insights
Last updated: October 23, 2026
Application No. 18/518,721

SEMICONDUCTOR STRUCTURE INCLUDING A BIT LINE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §102§103
Filed
Nov 24, 2023
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
741 granted / 1091 resolved
At TC average
Strong +30% interview lift
Without
With
+29.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
86 currently pending
Career history
1203
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
45.7%
+5.7% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
22.8%
-17.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1091 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to amendment filed 8/4/2026. Claims 1-16 are pending. Claims 11-16 have been withdrawn. Claims 1-3 and 10 have been amended. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 6-7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2012/0217631 A1 (Kim). PNG media_image1.png 870 728 media_image1.png Greyscale In re claim 1, Kim discloses (e.g. FIG. 30A) a semiconductor structure, comprising: a base structure 200 having a top surface; a bit line structure 224 disposed on the top surface of the base structure 200; and a spacer 320,250,244 disposed around the bit line structure and on top surface of the base structure 200, and including a first layer 320, a second layer 250 and a third layer 244, wherein the third layer 244 is disposed over the second layer 250 and a width of the third layer 244 is substantially equal to a width of the second layer 250; wherein a bottom surface of the first layer 320 is aligned with a bottom surface of the second layer 250; wherein a top surface of the first layer 320 is aligned with a top surface of the third layer 244; wherein a length of the first layer 320 is equal to a sum of a length of the second layer 250 and a length of the third layer 244. In re claim 2, Kim discloses (FIG. 30A) wherein the base structure 200 includes a base portion 200 and an active area 208 in the base portion (¶ 105), wherein the bit line structure 224 (middle bit line structure 224 in FIG. 30A) is electrically connected to the active area 208 through a conductor 218 (¶ 109), wherein a bottom surface of the conductor 218, the bottom surface of the first layer 320, and the bottom surface of the second layer 250 are aligned with each other. In re claim 3, Kim discloses (e.g. FIG. 30A) wherein the base structure 200 includes a base portion 200 and an active area 208 in the base portion (¶ 105), wherein the bit line structure 224 (left or right bit line structure in FIG. 30A) is electrically insulated from the active area 208 through an insulator 216 (¶ 109), wherein a bottom surface of the insulator 216, the bottom surface of the first layer 320, and the bottom surface of the second layer 250 are aligned with each other. In re claim 4, Kim discloses (e.g. FIG. 30A) wherein the first layer 320 is interposed between the second layer 250 and the bit line structure 224, and a width of the first layer 320 is less than a width of the second layer 250 (see FIG. 30A, ¶ 235). In re claim 6, Kim discloses (e.g. FIG. 30A) wherein a material of the first layer 320 (e.g. silicon nitride, ¶ 234) is different from a material of the second layer 250 (air, ¶ 116). In re claim 7, Kim discloses (e.g. FIG. 30A) wherein the first layer 320 is interposed between the third layer 244 and the bit line structure 224 and a width of the first layer 320 is less than a width of the third layer 244 (see FIG. 30A, ¶ 235). In re claim 9, Kim discloses (e.g. FIG. 30A) wherein a material of the first layer 320 (e.g. silicon nitride, ¶ 234) is same as a material of the third layer 244 (silicon nitride, ¶ 114). In re claim 10, Kim discloses (e.g. FIG. 30A) wherein the bit line structure 224 includes a main portion 220 and a cap portion 222 disposed on the main portion 220 (¶ 110), wherein an elevation of a top surface of the main portion 220 is lower than an elevation of a top surface of the second layer 250 of the spacer, wherein a top surface of the cap portion 222, the top surface of the first layer 320, and the top surface of the third layer 244 are aligned with each other. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 4 and 7 above, and further in view of Ji et al. US 2021/0035984 A1 (Ji). In re claims 5 and 8, Kim discloses (e.g. FIG. 30A) the first layer 320 has a relatively narrow thickness (¶ 235) and is shown to have a width that is less than a width of the second layer 250 and the third layer 244 in FIG. 30A. Kim does not explicitly disclose the width of the first layer 320 is substantially equal to one half of the width of the second layer 250 and the third layer 244. However, Ji discloses (e.g. FIG. 4A) a multilayered spacer structure 216 around a bit line structure 213,214, wherein a thinner layer S1 is approximately 1 nm thick and a thicker layer S22 is thicker than 2 nm (¶ 73-74). Consequently, the width of the thin layer S1 is substantially equal to one half of the width of the thicker layer S22 when S1 is 1 nm and S22 is about 2 nm. Ji teaches controlling the thicknesses to form a thicker low-k spacer layer S22 to reduce the parasitic capacitance (¶ 74). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kim’s spacer structure with a thin first layer 320 and thick low-k air space layer 250 such that the width of the first layer 320 is substantially equal to one half of the width of the second layer 250 and the third layer 244 to control the thickness of the spacer layers to obtained desired parasitic capacitance as taught by Ji. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Response to Arguments Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
Read full office action

Prosecution Timeline

Nov 24, 2023
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102, §103
Aug 04, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.8%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1091 resolved cases by this examiner. Grant probability derived from career allowance rate.

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