DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of invention I (claims 1-10) in the reply filed on 6/2/2026 is acknowledged.
Claims 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/2/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mun et al. US 2022/0059543 A1 (Mun).
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In re claim 1, Mun discloses (e.g. FIGs. 6A-6C) a semiconductor structure, comprising:
a base structure 201;
a bit line structure 213+214 disposed over the base structure; and
a spacer 215U,215L disposed around the bit line structure, and including a first layer 216, a second layer and a third layer (in a first interpretation, “second layer” correspond to upper portion of 218 and “third layer” correspond to 219+220 above 218), wherein the third layer 219+220 is disposed over the second layer 218 and a width of the third layer (width of 219+220 along C-C’) is substantially equal to a width of the second layer (width of 218 along D-D’).
In a second interpretation, “second layer” correspond to lower portion of 217 and “third layer” correspond to upper portion of 217, wherein the third layer (upper portion of 217) is disposed over the second layer (lower portion of 217) and a width of the third layer (upper portion of 217) is substantially equal to a width of the second layer (upper portion of 217).
In a third interpretation, as shown in FIG. 6C, “second layer” correspond AG and “third layer” correspond to AGC, wherein the third layer AGC is disposed over the second layer AG and a width of the third layer AGC is substantially equal to a width of the second layer AG.
In re claim 2, Mun discloses (FIGs. 6A-6C) wherein the base structure 201 includes a base portion 203 and an active area 209 in the base portion, wherein the bit line structure 213++214 is electrically connected to the active area through a conductor 212.
In re claim 3, Mun discloses (e.g. FIGs. 6A-6C) wherein the base structure 201 includes a base portion 203 and an active area 210 in the base portion, wherein the bit line structure 213+214 (outer bit line structures) is electrically insulated from the active area 210 through an insulator 204 (¶ 85).
In re claim 4, Mun discloses (e.g. FIGs. 6A-6C) wherein the first layer 216 is interposed between the second layer (218, or lower portion of 217, or AG) and the bit line structure 213+214, and a width of the first layer 216 is less than a width of the second layer (218, or lower portion of 217, or AG; ¶ 93).
In re claim 5, Mun discloses (in the second interpretation as annotated for FIG. 6B above) wherein the width of the first layer 216 is substantially equal to one half of the width of the second layer (lower portion of 217, ¶ 93).
In re claim 6, Mun discloses (e.g. FIG. 6A-6C) wherein a material of the first layer 216 (e.g. silicon nitride, ¶ 93) is different from a material of the second layer (lower portion of 217 in second interpretation formed of SiC, ¶ 92; or air gap AG in third interpetation).
In re claim 7, Mun discloses (e.g. FIGs. 6A-6C) wherein the first layer 216 is interposed between the third layer (219+220, or upper portion of 217, or AGC) and the bit line structure 213+214, and a width of the first layer 216 is less than a width of the third layer (219+220, or upper of 217, or AGC; ¶ 93).
In re claim 8, Mun discloses (in the second interpretation as annotated for FIG. 6B above) wherein the width of the first layer 216 is substantially equal to one half of the width of the third layer (upper portion of 217, ¶ 93).
In re claim 9, Mun discloses (e.g. FIG. 6C) wherein a material of the first layer 216 (e.g. silicon nitride, ¶ 93) is same as a material of the third layer AGC (silicon nitride, ¶ 242).
In another interpretation of FIG. 6A, the first layer is layer 217, the second layer is layer 219+220, the third layer is 218. As such, a material of the first layer 217is same as a material of the third layer 220 (¶ 92).
In re claim 10, Mun discloses (e.g. FIG. 6C, third interpretation) wherein the bit line structure 213+214 includes a main portion 213 and a cap portion 214 disposed on the main portion 213 (¶ 85), wherein an elevation of a top surface of the main portion 213 is lower than an elevation of a top surface of the second layer AG of the spacer.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,610,535. Although the claims at issue are not identical, they are not patentably distinct from each other because current pending claims are anticipated by the patented claims. More specifically,
Pending claim 1 is anticipated by claim 1 of US 12,610,535.
Pending claim 2 is anticipated by claim 2 of US 12,610,535.
Pending claim 3 is anticipated by claim 2 of US 12,610,535.
Claim 4-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. U.S. Patent No. 12,610,535 in view of Mun.
Although the claims of U.S. Patent No. 12,610,535 does not specifically recites the width, material, and elevation as recited in claims 4-10, these features are obvious in view of Mun as detailed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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