DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 12-16, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (PN 10,984,878, of record) in view of Kirihata et al. (PN 11,329,836, of record).
Regarding claim 1, Chang et al. discloses, as shown in Figures 2 and 4, a memory array comprising:
a continuous active region (OD, 410) extending along a direction;
a first bit cell (102) comprising a first programming device (202) and a first reading device (204) defined on the continuous active region (Figure 2);
a first programing word line (WLP) coupled to a gate of the first programing device;
a first reading word line (WLR) coupled to the gate of the first reading devices; and
a bit line (BL), wherein a first reading devices is coupled between a first source/drain node of the first programing device and the bit line
Chang et al. does not disclose the first reading device defined as a pair of the first reading devices. However, Kirihara et al. discloses a memory array having a Physical Unclonable Function (PUF) structure includes an array of twin cell (211,212) connected in series between the bit line and the source line when performing the read operation. Note Figure 2 of Kirihata et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to replace the first reading transistor with a pair of reading transistors, such as taught by Kirihara et al. in order to further improve the reliability of memory cells under high voltage operation and/or to further reduce leakage current in the off-state.
Regarding claim 2, Chang et al. and Kirihata et al. do not disclose the first programming device is defined between the pair of first reading devices. However, it is a common practice to place the first programming device between the pair of first reading devices for symmetrical balance. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to place the first programming device of Chang et al. and Kirihata et al. between the pair of first reading devices in order to improve the performance of the device.
Regarding claim 4, Chang et al. discloses a plurality of bit cells (102) having a second bit cell defined on the continuous active region and arranged along the direction, wherein the second bit cell comprises a second programing device and a second reading devices along the direction. Kirihata et al. also discloses a plurality of bit cells having an array of twin cell (211,212). The combination of Chang et al. and Kirihata et al. inventions disclose a second bit cell defined on the continuous active region and arranged along the direction, wherein the second bit cell comprises a second programing device and a pair of second reading devices along the direction.
Regarding claim 5, Chang et al. and Kirihata et al. do not disclose a second one of the pair of first reading devices is coupled between a second source/drain node of the first programing device and the bit line. However, it is a common practice to connect the second one of the pair of first reading devices is coupled between a second source/drain node of the first programing device and the bit line for symmetrical balance. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was connect the second one of the pair of first reading devices of Chang et al. and Kirihata et al. coupled between a second source/drain node of the first programing device and the bit line in order to improve the performance of the device.
Regarding claim 12, Chang et al. discloses, as shown in Figures 2 and 4, a memory array comprising:
a first bit cell (102) comprising a first programming device (202) and a first reading device (204) defined on the continuous active region (OD, 410) along a direction (Figure 2);
a first programing word line (WLP) coupled to a gate of the first programing device;
a first reading word line (WLR) coupled to the gate of the first reading devices; and
a bit line (BL), wherein a first reading devices is coupled between a first source/drain node of the first programing device and the bit line.
Chang et al. does not disclose the first reading device defined as a pair of the first reading devices. However, Kirihara et al. discloses a memory array having a Physical Unclonable Function (PUF) structure includes an array of twin cell (211,212) connected in series between the bit line and the source line when performing the read operation. Note Figure 2 of Kirihata et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to replace the first reading transistor with a pair of reading transistors, such as taught by Kirihara et al. in order to further improve the reliability of memory cells under high voltage operation and/or to further reduce leakage current in the off-state. It is a common practice to place the first programming device between the pair of first reading devices for symmetrical balance. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to place the first programming device of Chang et al. and Kirihata et al. between the pair of first reading devices in order to improve the performance of the device.
Regarding claim 13, Chang et al. and Kirihata et al. do not disclose a second one of the pair of first reading devices is coupled between a second source/drain node of the first programing device and the bit line. However, it is a common practice to connect the second one of the pair of first reading devices is coupled between a second source/drain node of the first programing device and the bit line for symmetrical balance. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was connect the second one of the pair of first reading devices of Chang et al. and Kirihata et al. coupled between a second source/drain node of the first programing device and the bit line in order to improve the performance of the device.
Regarding claim 14, Chang et al. and Kirihata et al. disclose a gate of first programming transistor comprises a first gate dielectric layer configured to be broken down to present a first logic state.
Regarding claim 15, Chang et al. and Kirihata et al. disclose respective gates of the pair of reading transistors are coupled to a reading word line.
Regarding claim 16, Chang et al. and Kirihata et al. disclose respective gates of the pair of reading transistors and a gate of the first programming transistor are parallel to one another and extend along a second direction that is perpendicular to the direction of the continuous active region.
Regarding claim 21, Chang et al. and Kirihata et al. disclose the pair of reading devices comprises a pair of n-type transistors.
Regarding claim 22, Chang et al. and Kirihata et al. disclose at least one of the pair of reading devices are in series with the first programming device.
Regarding claim 23, Chang et al. discloses, as shown in Figures 2 and 4, a memory array comprising:
a first bit cell (102) comprising a first programming device (202) and a first reading device (204) defined on the continuous active region (OD, 410) along a direction (Figure 2);
a first programing word line (WLP) coupled to a gate of the first programing device;
a first reading word line (WLR) coupled to the gate of the first reading devices; and
a bit line (BL), wherein a first reading devices is coupled between a first source/drain node of the first programing device and the bit line; and
a reading word line (WLR) disposed over the reading transistor.
Chang et al. does not disclose the first reading device defined as a pair of the first reading devices. However, Kirihara et al. discloses a memory array having a Physical Unclonable Function (PUF) structure includes an array of twin cell (211,212) connected in series between the bit line and the source line when performing the read operation. Note Figure 2 of Kirihata et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to replace the first reading transistor with a pair of reading transistors, such as taught by Kirihara et al. in order to further improve the reliability of memory cells under high voltage operation and/or to further reduce leakage current in the off-state. It is a common practice to place the first programming device between the pair of first reading devices for symmetrical balance. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to place the first programming device of Chang et al. and Kirihata et al. between the pair of first reading devices in order to improve the performance of the device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (PN 10,984,878, of record) in view of Kirihata et al. (PN 11,329,836, of record) and further in view of Liaw (PN 10,460,794, of record).
Regarding claim 3, Chang et al. and Kirihata et al. disclose the claimed invention including the memory array as explained in the above rejection. Chang et al. and Kirihata et al. do not disclose an isolation structure surrounding the continuous active region. However, Liaw discloses a memory having an isolation structure surrounding the active region. Note Figure of Liaw. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the array of Chang et al. and Kirihata et al. having an isolation structure surrounding the active region, such as taught by Liaw in order to isolate one array from another.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (PN 10,984,878, of record) in view of Kirihata et al. (PN 11,329,836, of record) and further in view of Lin et al. (CN102376718B, of record).
Regarding claim 6, Chang et al. and Kirihata et al. disclose the claimed invention including the memory array as explained in the above rejection. Chang et al. discloses a plurality of bit cells (102) having a second bit cell defined on the continuous active region and arranged along the direction, wherein the second bit cell comprises a second programing device and a second reading devices along the direction. Kirihata et al. also discloses a plurality of bit cells having an array of twin cell (211,212). Chang et al. and Kirihata et al. do not disclose the array further comprising: a first pair of voltage-relaxing devices, wherein the first programing device is between the first pair of voltage-relaxing devices, and the voltage-relaxing devices are between the pair of first reading devices. However, Lin et al. discloses in Figures 8-10, each group of bit lines 16 includes two bit lines 14 that connect to the same sub memory array 30 of the cells (32, 34), that is to connect to the same bit line 14. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the array of Chang et al. and Kirihata et al. having a first pair of voltage-relaxing devices, wherein the first programing device is between the first pair of voltage-relaxing devices, and the voltage-relaxing devices are between the pair of first reading devices, such as taught by Lin et al. in order to order to reduce the whole layout area.
Regarding claim 7, Chang et al. discloses a plurality of bit cells (102) having a second bit cell defined on the continuous active region and arranged along the direction, wherein the second bit cell comprises a second programing device and a second reading devices along the direction. Kirihata et al. also discloses a plurality of bit cells having an array of twin cell (211,212). The combination of Chang et al., Kirihata et al. and Lin et al. disclose a voltage-relaxing line coupled to gates of the first pair of voltage-relaxing devices, wherein a first one of the voltage-relaxing devices is coupled between the first source/drain node of the first programing device and the first one of the pair of first reading devices, and a second one of the voltage-relaxing devices is coupled between a second source/drain node of the first programing device and a second one of the pair of first reading devices.
Regarding claim 8, Chang et al. discloses a plurality of bit cells (102) having a second bit cell defined on the continuous active region and arranged along the direction, wherein the second bit cell comprises a second programing device and a second reading devices along the direction. Kirihata et al. also discloses a plurality of bit cells having an array of twin cell (211,212). The combination of Chang et al., Kirihata et al. and Lin et al. disclose a second pair of voltage-relaxing devices defined between the pair of first reading devices and the first pair of voltage-relaxing devices.
Claim(s) 9-11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (PN 10,984,878, of record) in view of Kirihata et al. (PN 11,329,836, of record) and further in view of Hsieh (US 2017/0352670, of record).
Regarding claims 9 and 17, Chang et al. and Kirihata et al. disclose the claimed invention including the memory array as explained in the above rejection. Chang et al. and Kirihata et al. do not disclose a first conductive via connecting a source/drain node of the first one of the pair of first reading devices to the bit line, and a second conductive via connecting a source/drain node of the second one of the pair of first reading devices to the bit line. It is a common practice to place the dielectric over the transistor and form the conductive vias in the dielectric to connect the transistor to the bit line / word line. Hsieh disclose a device having the conductive vias (150a-150f) connecting the source/drain node to the bit line (212). Note Figure 3L of Hsieh. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Chang et al. and Kirihata et al. having the conductive vias connecting the source/drain node to the bit line, such as taught by Hsieh in order to provide the interconnection to perform the desired function.
Regarding claim 10, Chang et al., Kirihata et al. and Hsieh disclose the first conductive via and the second conductive via are defined through the continuous active region.
Regarding claim 11, Chang et al. and Kirihata et al. disclose the claimed invention including the memory array as explained in the above rejection. Chang et al. and Kirihata et al. do not disclose comprising a dummy gate structure over an edge portion of the continuous active region. However, Hsieh discloses a device having a dummy gate structure (144a) over an edge portion of the active region. Note Figure 3K and [0028] of Hsieh. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Chang et al. and Kirihata et al. having a dummy gate structure over an edge portion of the active region, such as taught by Hsieh in order to improve the planar surface of the device.
Response to Arguments
Applicant's arguments filed 07/08/2026 have been fully considered but they are not persuasive.
It is argued, at pages 6-8 of the Remarks, that twin cells (211,212) are not reading devices. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Chang et al. does not disclose the first reading device (204) defined as a pair of the first reading devices. Kirihara et al. discloses a memory array having a Physical Unclonable Function (PUF) structure includes an array of twin cell (211,212) connected in series between the bit line and the source line when performing the read operation (Col. 3, line 63 – Col. 4, line 47). Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to replace the first reading transistor with a pair of reading transistors, such as taught by Kirihara et al. in order to further improve the reliability of memory cells under high voltage operation and/or to further reduce leakage current in the off-state.
Also, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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