DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 13 May 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the AR widths in claim 21 must be shown or the features canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 13, and 21 are objected to because of the following informalities: The term --dopant type-- was erroneously changed to --dopant-type-- with a hyphen, which is an adjective construction. Appropriate correction is required.
Claims 11 and 14-17 are objected to because of the following informalities: The term --of the-- in line 1 is written twice in a row. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 13-15, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al (US 20220302134 A1, hereinafter “Hwang”), in view of Yamagami (US 20220108992 A1, hereinafter “Yamagami”).
Regarding Claim 1 - Hwang discloses a static random access memory (SRAM) comprising: CFET stacks including first, second (SRAM circuit [0040-0041], Fig. 2A-C), third, and fourth CFET stacks (SRAM circuit [0091-0092], Fig. 6A), each CFET stack including a first active region (AR) having a first dopant-type (240c&d [0050], Figs. 2B and 2C) stacked in a first direction (D1, annotated Fig. 2B) on a second AR having a second dopant type different than the first dopant type (240a&b [0045], Figs. 2B and 2C), each CFET stack representing a complementary field-effect transistor (CFET) architecture (Stacked PMOS and NMOS [0042] and Figs. 2B and 2C); an upper half of a third CFET stack (e.g. 3rd in F2 in annotated Fig. 6A); and a lower half of a fourth CFET stack (e.g. 4th in F1 in annotated Fig. 6A); and wherein the first and second CFET stacks including field-effect transistors (FETs) that comprise a latch of the SRAM (PU1, PU2, PD1, and PD2 [0041] and Fig. 2A); wherein the first CFET stack further including FETs that comprise a first port of the SRAM (PG1 [0041] and Fig. 2B); wherein the second CFET stack further including FETs that comprise a second port of the SRAM (PG2 [0041] and Fig. 2B).
Hwang fails to disclose the first CFET stack further including FETs that comprise a third port of the SRAM, the second CFET stack further including FETs that comprise a fourth port of the SRAM, the lower half of the fourth CFET stack including FETs that comprise a fifth port of the SRAM, and the upper half of the third CFET stack including FETs that comprise a sixth port of the SRAM.
However, Yamagami discloses the first CFET stack further including FETs that comprise a third port of the SRAM (PG3 [0092] and Fig. 8B), the second CFET stack further including FETs that comprise a fourth port of the SRAM (PG4 [0092] and Fig. 8B), the upper half of the third CFET stack including FETs that comprise a sixth port of the SRAM (RPD1 and RPG1, Yamagami [0111] and Fig. 10B).
Yamagami fails to expressly disclose the lower half of the fourth CFET stack including FETs that comprise a fifth port of the SRAM. However, a fourth CFET stack represents a duplication of parts, and therefore, a prima facie case of obviousness. See MPEP 2144.04(VI)(B). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to add CFET stacks for the desired number of ports using a duplication of parts.
Yamagami discloses an analogous SRAM to Hwang. Yamagami teaches the inclusion of third and fourth data ports for the benefits of data writing, data holding, and data reading by multiple word lines (e.g. WLA and WLB, Yamagami [0091]). Therefore, it would have been obvious to one of ordinary skill in the art to include third and fourth data ports for the benefits of data writing, data holding, and data reading by multiple word lines.
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Regarding Claim 2 - Hwang modified by Yamagami discloses all the limitations of claim 1.
The combination of Hwang and Yamagami further discloses the latch of the of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0038] and Fig. 2A); the first PFET and the first NFET are in the first CFET stack (PU1 and PD1 are in the left stack in Figs. 2B and 2C); and the second PFET and the second NFET are in the second CFET stack (PU2 and PD2 are in the right stack in Figs. 2B and 2C).
Regarding Claim 3 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the first port includes a third NFET that is in the first CFET stack (PG1, Hwang [0038] and Fig. 2B); the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Fig. 2B); and the third NFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Fig. 2B).
Regarding Claim 4 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the second port includes a third NFET that is in the second CFET stack (PG2, Hwang [0038] and Fig. 2B); the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Fig. 2B); and the third NFET is aligned with each of the first PFET and the first NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Fig. 2B).
Regarding Claim 8 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the sixth port includes third and fourth NFETs that are in the upper half of the first CFET stack (RPD1 and RPG1, Yamagami [0111] and Fig. 10A); the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Fig. 2B); and the third NFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Fig. 2B); and the fourth NFET is aligned with each of the first PFET and the first NFET relative to the third direction (Aligned in D3, as in annotated Fig. 2B).
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Regarding Claim 13 - Hwang discloses a static random access memory (SRAM) comprising: first, second (SRAM circuit [0040-0041], Fig. 2A-C), and third CFET stacks (SRAM circuit [0091-0092], Fig. 6A), each CFET stack including a first active region (AR) having a first dopant type (240c&d [0050], Figs. 2B and 2C) stacked in a first direction (D1, annotated Fig. 2B) on a second AR having a second dopant type different than the first dopant type (240a&b [0045], Figs. 2B and 2C), each CFET stack representing a complementary field-effect transistor (CFET) architecture (Stacked PMOS and NMOS [0042] and Figs. 2B and 2C); and wherein the first and second CFET stacks including field-effect transistors (FETs) that comprise a latch of the SRAM (PU1, PU2, PD1, and PD2 [0041] and Fig. 2A); wherein the first CFET stack further including FETs that comprise a first port of the SRAM (PG1 [0041] and Fig. 2B); wherein the second CFET stack further including FETs that comprise a second port of the SRAM (PG2 [0041] and Fig. 2B).
Hwang fails to disclose the first CFET stack further including FETs that comprise a third port of the SRAM, the second CFET stack further including FETs that comprise a fourth port of the SRAM, and the third CFET stack including FETs that comprise fifth and sixth ports of the SRAM.
However, Yamagami discloses the first CFET stack further including FETs that comprise a third port of the SRAM (PG3 [0092] and Fig. 8B), the second CFET stack further including FETs that comprise a fourth port of the SRAM (PG4 [0092] and Fig. 8B), and the third CFET stack including FETs that comprise a fifth port of the SRAM (RPD1 and RPG1, Yamagami [0111] and Fig. 10B).
Yamagami fails to expressly disclose the third stack includes FETs that comprise a sixth port of the SRAM. However, the upper and lower FETs can be independently connected, just as the upper and lower FETs of Hwang (e.g. PU1 and PU2 only in upper layer and PG1 and PG2 only in lower layer, Hwang [0041] and Figs. 2B and 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming fifth and sixth ports independently in the third CFET stack.
Yamagami discloses an analogous SRAM to Hwang. Yamagami teaches the inclusion of additional data ports for the benefits of data writing, data holding, and data reading by multiple word lines (e.g. WLA and WLB, Yamagami [0091]). Therefore, it would have been obvious to one of ordinary skill in the art to include third and fourth data ports for the benefits of data writing, data holding, and data reading by multiple word lines.
Regarding Claim 14 - Hwang modified by Yamagami discloses all the limitations of claim 13.
The combination of Hwang and Yamagami further discloses the latch of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0038] and Fig. 2A); the first PFET and the first NFET are in the first CFET stack (PU1 and PD1 are in the left stack in Hwang Figs. 2B and 2C); the second PFET and the second NFET are in the second CFET stack (PU2 and PD2 are in the right stack in Hwang Figs. 2B and 2C); the first port includes a third NFET that is in the first CFET stack (PG1, Hwang [0038] and Fig. 2B); the first to third CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Hwang Fig. 2B); and the third NFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Hwang Fig. 2B).
Regarding Claim 15 - Hwang modified by Yamagami discloses all the limitations of claim 13.
The combination of Hwang and Yamagami further discloses the latch of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0038] and Fig. 2A); the first PFET and the first NFET are in the first CFET stack (PU1 and PD1 are in the left stack in Hwang Figs. 2B and 2C); the second PFET and the second NFET are in the second CFET stack (PU2 and PD2 are in the right stack in Hwang Figs. 2B and 2C); the second port includes a third NFET that is in the second CFET stack (PG2, Hwang [0038] and Fig. 2B); the first to third CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Hwang Fig. 2B); and the third NFET is aligned with each of the first PFET and the first NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Hwang Fig. 2B).
Regarding Claim 21 - Hwang discloses a static random access memory (SRAM) comprising: CFET stacks including first, second (SRAM circuit [0040-0041], Fig. 2A-C), third, and fourth CFET stacks (SRAM circuit [0091-0092], Fig. 6A), each CFET stack including a first active region (AR) having a first dopant type (240c&d [0050], Figs. 2B and 2C) stacked in a first direction (D1, annotated Fig. 2B) on a second AR having a second dopant type different than the first dopant type (240a&b [0045], Figs. 2B and 2C), each CFET stack representing a complementary field-effect transistor (CFET) architecture (Stacked PMOS and NMOS [0042] and Figs. 2B and 2C); and wherein the first and second CFET stacks including field-effect transistors (FETs) that comprise a latch of the SRAM (PU1, PU2, PD1, and PD2 [0041] and Fig. 2A); wherein the first CFET stack further including FETs that comprise a first port of the SRAM (PG1 [0041] and Fig. 2B); wherein the second CFET stack further including FETs that comprise a second port of the SRAM (PG2 [0041] and Fig. 2B).
Hwang fails to disclose the first CFET stack further including FETs that comprise a third port of the SRAM, the second CFET stack further including FETs that comprise a fourth port of the SRAM, the fourth CFET stack including FETs that comprise a fifth port of the SRAM, and the third CFET stack including FETs that comprise a sixth port of the SRAM; wherein the first and second ARs of the first and second CFET stacks have a first width relative to a second direction perpendicular to the first direction; wherein the first and second ARs of the third and fourth CFET stacks have a second width relative to the second direction, the second width being greater than the first width.
However, Yamagami discloses the first CFET stack further including FETs that comprise a third port of the SRAM (PG3 [0092] and Fig. 8B), the second CFET stack further including FETs that comprise a fourth port of the SRAM (PG4 [0092] and Fig. 8B), the upper half of the third CFET stack including FETs that comprise a sixth port of the SRAM (RPD1 and RPG1, Yamagami [0111] and Fig. 10B).
Yamagami fails to expressly disclose the lower half of the fourth CFET stack including FETs that comprise a fifth port of the SRAM. However, a fourth CFET stack represents a duplication of parts, and therefore, a prima facie case of obviousness. See MPEP 2144.04(VI)(B). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to add CFET stacks for the desired number of ports using a duplication of parts.
Yamagami discloses an analogous SRAM to Hwang. Yamagami teaches the inclusion of third and fourth data ports for the benefits of data writing, data holding, and data reading (Yamagami [0091]). Therefore, it would have been obvious to one of ordinary skill in the art to include third and fourth data ports for the benefits of data writing, data holding, and data reading.
Yamagami fails to disclose the third and fourth CFET stacks have a second width relative to the second direction greater than the width of the first and second ARs of the first and second CFET stacks. However, it is well-known in the industry that width affects electrical characteristics (i.e. MOSFET drain current is proportional to width divided by length. See, for example, the Triode Region and Saturation Region equations found here: https://qiita.com/digital_amplifier_1/items/1cc099d780ddbc5c759d, accessed 6 July 2026). Therefore, optimizing channel (active region (or AR)) width is a matter of routine optimization, and a prima facie case of obviousness. See MPEP 2144.05(II). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to optimize the AR widths for the desired electrical characteristics of each MOSFET.
Regarding Claim 22 - Hwang modified by Yamagami discloses all the limitations of claim 21.
The combination of Hwang and Yamagami further discloses the first and second CFET stacks are adjacent to each other relative to the second direction (Spaced apart in D2, as in annotated Hwang Fig. 2B).
Regarding Claim 23 - Hwang modified by Yamagami discloses all the limitations of claim 22.
The combination of Hwang and Yamagami further discloses relative to the second direction: the first CFET stack is between the second CFET stack and the third CFET stack; and the second CFET stack is between the first CFET stack and the fourth CFET stack (3rd and 4th, annotated Hwang Fig. 6A).
Claims 5-7, 9-12, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al (US 20220302134 A1, hereinafter “Hwang”), in view of Yamagami (US 20220108992 A1, hereinafter “Yamagami”), and further in view of Camarota (EP 3028304 B1, hereinafter “Camarota”).
Regarding Claim 5 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Hwang Fig. 2B); and the third PFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, , as in annotated Hwang Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the third port includes a third PFET that is in the first CFET stack.
However, Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
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Regarding Claim 6 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, , as in annotated Hwang Fig. 2B); and the third PFET is aligned with each of the first PFET and the first NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, , as in annotated Hwang Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the fourth port includes a third PFET that is in the second CFET stack.
However, Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
Regarding Claim 7 - Hwang modified by Yamagami discloses all the limitations of claim 2.
The combination of Hwang and Yamagami further discloses the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Fig. 2B); and the third PFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Fig. 2B); and the fourth PFET is aligned with each of the first PFET and the first NFET relative to the third direction (Aligned in D3, as in annotated Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the fifth port includes third and fourth PFETs that are in the lower half of the fourth CFET stack.
However, the PFETs of the SRAM may be in the lower layer of each stack (alternative structure of Yamagami [0080]), and Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
Regarding Claim 9 - Hwang modified by Yamagami discloses all the limitations of claim 1.
The combination of Hwang and Yamagami further discloses the latch of the of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0041] and Fig. 2A); the first port includes a third NFET that is in the first CFET stack (PG1, Hwang [0038] and Fig. 2B); the sixth port includes a fourth NFET that is in the upper half of the third CFET stack (RPD1 or RPG1, Yamagami [0111] and Fig. 10A); the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Fig. 2B); and the third and fourth NFETs and the third and fourth PFETs are aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the fifth port includes a fourth PFET that is in the lower half of the fourth CFET stack.
However, the PFETs of the SRAM may be in the lower layer of each stack (alternative structure of Yamagami [0080]), and Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
Regarding Claim 10 - Hwang modified by Yamagami and Camarota discloses all the limitations of claim 9.
The combination of Hwang, Yamagami, and Camarota further discloses a gate structure formed around corresponding portions of the first and second AR regions in the second CFET stack and the second AR region in the lower half of the fourth CFET stack (The combination of 231b, 231f, and 255b form the gate of RPD1, PD2, and PU2, Yamagami [0126], [0131] and Figs. 12A and 12B); and wherein the gate structure represents a gate electrode that is coupled to each of the second NFET and the second and fourth PFETs (PD2 = NFET (Yamagami [0055]), PU2 = PFET (Yamagami [0055]), and RPD1 = PFET (112, Camarota [0025] and Fig. 1).
Regarding Claim 11 - Hwang modified by Yamagami discloses all the limitations of claim 1.
The combination of Hwang and Yamagami further discloses the latch of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0041] and Fig. 2A); the second port includes a third NFET that is in the second CFET stack (PG2, Hwang [0038] and Fig. 2B); the sixth port includes a fourth NFET that is in the upper half of the third CFET stack (RPD1 and RPG1, Yamagami [0111] and Fig. 10B, considered as an alteration by Yamagami, with NFETs in upper layer and PFETs in lower layer, Yamagami [0080]); the first to fourth CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (D2 in annotated Hwang Fig. 2B and X in Yamagami Fig. 10B); and the third and fourth NFETs and the third and fourth PFETs are aligned with each of the first PFET and the first NFET relative to a third direction perpendicular to each of the first and second directions (D3 in annotated Hwang Fig. 2B and Y in Yamagami Fig. 10B).
The combination of Hwang and Yamagami fails to expressly disclose the fifth port includes a fourth PFET that is in the lower half of the fourth CFET stack. The duplication of parts for a fifth port using Yamagami as a reference regarding claim 1 does not include PFETs.
However, Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1). Including PFETs in a fifth port is a prima facie case of obviousness by duplication of parts. See MPEP 2144.04(VI)(B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Hwang, Yamagami, and Camarota to include PFETs in a fifth port.
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang, Yamagami, and Camarota to include PFETs in a fifth SRAM port for the benefit of compact layout.
Regarding Claim 12 - Hwang modified by Yamagami and Camarota discloses all the limitations of claim 11.
The combination of Hwang, Yamagami, and Camarota further discloses a gate structure formed around corresponding portions of the first AR region in the lower half of the third CFET stack and the first and second AR regions in the first CFET stack and wherein the gate structure represents a gate electrode that is coupled to each of the first PFET and the first and fourth NFETs (The combination of 331a, 331c, 254a, and 255a form the gate of RPD2, PD1, and PU1, Yamagami [0144-0145], [0148] and Figs. 12A and 12B).
Regarding Claim 16 - Hwang modified by Yamagami discloses all the limitations of claim 13.
The combination of Hwang and Yamagami further discloses the latch of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0038] and Fig. 2A); the first PFET and the first NFET are in the first CFET stack (PU1 and PD1 are in the left stack in Hwang Figs. 2B and 2C); the second PFET and the second NFET are in the second CFET stack (PU2 and PD2 are in the right stack in Hwang Figs. 2B and 2C); the first to third CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Hwang Fig. 2B); and the third PFET is aligned with each of the second PFET and the second NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Hwang Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the third port includes a third PFET that is in the first CFET stack.
However, Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
Regarding Claim 17 - Hwang modified by Yamagami discloses all the limitations of claim 13.
The combination of Hwang and Yamagami further discloses the latch of the SRAM includes first and second P-type FETs (PFETs) and first and second N-type FETs (NFETs) (PU1, PU2, PD1, and PD2, Hwang [0038] and Fig. 2A);the first PFET and the first NFET are in the first CFET stack (PU1 and PD1 are in the left stack in Hwang Figs. 2B and 2C); the second PFET and the second NFET are in the second CFET stack (PU2 and PD2 are in the right stack in Hwang Figs. 2B and 2C); the first to third CFET stacks are spaced apart from each other relative to a second direction perpendicular to the first direction (Spaced apart in D2, as in annotated Hwang Fig. 2B); and the third PFET is aligned with each of the first PFET and the first NFET relative to a third direction perpendicular to each of the first and second directions (Aligned in D3, as in annotated Hwang Fig. 2B).
The combination of Hwang and Yamagami fails to disclose the fourth port includes a third PFET that is in the second CFET stack.
However, Camarota discloses third and fourth ports including PFETs (110 and 112, Camarota [0025] and Fig. 1).
Camarota discloses SRAM memory analogous to Hwang. Camarota teaches four input ports with two of each conductivity type for the benefit of more compact layout (Camarota [0018]). The port PFETs in the configuration of Camarota can be naturally placed in the dummy positions of Hwang on the same level (F2 in Hwang Fig. 2C) as the other PFET in each of the first two CFET stacks (as shown in Hwang Fig. 2C). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hwang and Camarota to form four input ports with two of each conductivity type, placing the two port PFETs of Camarota in the dummy positions of Hwang for the benefit of compact layout.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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