DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
Claim 1 recites “the first epitaxial layer comprising a profile resembles a heptagon” in line 7, and “the second epitaxial layer comprising a profile resembles an octagon” in lines 10-11 (emphases added).
Claim 11 recites “a shape of the second semiconductor layer in a first cross-sectional view resembles an heptagon” in lines 1-2 (emphasis added).
The Examiner suggests the following amendment to correct apparent grammatical errors:
1. A method, comprising:
forming a fin-shaped active region protruding from a substrate;
forming a gate stack over a channel region of the fin-shaped active region;
recessing a source/drain region of the fin-shaped active region to form a source/drain trench;
performing a first epitaxial growth process to form a first epitaxial layer in the source/drain trench, the first epitaxial layer comprising a profile that resembles a heptagon shape in a first cross-sectional view;
performing a second epitaxial growth process to form a second epitaxial layer in the source/drain trench and on the first epitaxial layer, the second epitaxial layer comprising a profile that resembles an octagon shape in the first cross-sectional view; and
forming a source/drain contact over and electrically coupled to the first and second epitaxial layers.
11. The method of claim 9, wherein a shape of the second semiconductor layer in a first cross-sectional view resembles a heptagon and comprises two substantially vertical sidewalls.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (PG Pub. No. US 2016/0027918 A1).
Regarding claim 9, Kim teaches a method, comprising:
forming a source/drain trench (¶ 0083: 350) in a source/drain region (11D: SR and/or DR);
forming a first semiconductor layer (¶ 0083: 384) to fill a bottom portion of the source/drain trench (fig. 11E: 384 at least partially fills bottom of 350);
forming a second semiconductor layer (¶ 0083: 384 and/or 386) on the first semiconductor layer and in the source/drain trench (fig. 11E: 384/386 formed on layer 382 and in trench 350); and
depositing a third semiconductor layer (¶ 0083: 386 and/or 388) extending along sidewall and top surfaces of the second semiconductor layer (fig. 11E: 386/388 formed along side and top surfaces of 384/386), wherein the third semiconductor layer has a non-uniform deposition thickness and has a substantially planar top surface (fig. 11E: at least layer 388 includes a non-uniform thickness and a planar topmost surface).
Regarding claim 10, Kim teaches the method of claim 9, further comprising:
forming a fourth semiconductor layer (¶ 0077: 390) extending along sidewall and top surfaces of the third semiconductor layer (fig. 11E: 390 extends along side and top surfaces of 386/388), wherein the fourth semiconductor layer has a uniform deposition thickness (fig. 11E: 390 has a substantially uniform thickness).
Regarding claim 13, Kim teaches the method of claim 9, further comprising:
forming a dielectric structure (¶ 0077: 410) over the third semiconductor layer (fig. 11F: 410 formed over 388);
forming a source/drain contact trench (¶ 0113: contact hole) extending through the dielectric structure (fig. 11G: unlabeled contact hole formed in 410);
converting a portion of the second semiconductor layer and a portion of the third semiconductor layer to a silicide layer (¶ 0089: portions of 386 and 388 converted to metal silicide 430); and
forming a source/drain contact (¶ 0087: 440) on the silicide layer and in the source/drain contact trench (fig. 11G: 440 formed on 430 and in unlabeled contact hole).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 9 above, and further in view of Yoo et al. (PG Pub. No. US 2016/0079367 A1).
Regarding claim 11, Kim teaches the method of claim 9, wherein a shape of the second semiconductor layer in a first cross-sectional view resembles a polygon (Kim, fig. 11E: cross-section of 386 and/or 388 resembles a polygonal shape).
Kim does not teach the second semiconductor layer resembling a heptagon and comprises two substantially vertical sidewalls.
Yoo teaches a semiconductor layer (¶ 0040: 210 and/or 220) resembling a heptagon (¶ 0075, fig. 7: 210/210 include hexagonal cross-section).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second semiconductor layer of Kim to resemble a heptagon, as a means to resist short channel effect and provide higher drive current at low voltages (Yoo, ¶ 0004).
In addition, configuring the heptagonal semiconductor layer to further include two substantially vertical sidewalls would involve nothing more than routine skill. The Examiner asserts that a person of ordinary skill in the art would recognize that heptagonal semiconductor layers could be provided with or without two substantially vertical sidewalls, which would amount to nothing more that a change in shape. Absent persuasive evidence that the particular shape of the claimed second semiconductor layer is significant, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 12, Kim in view of Yoo teaches the method of claim 11, wherein a shape of the second semiconductor layer in a second cross-sectional view resembles a rectangle (Yoo, fig. 6: 220 comprises a rectangular shape in a second cross-sectional view).
Claims 14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin et al. (PG Pub. No. US 2020/0105621 A1)
Regarding claim 14, Kim teaches a method, comprising:
receiving a workpiece having an active region (¶ 0018: AF and/or ACT) over a semiconductor substrate (¶ 0077: 310) and a gate structure (¶ 0098: 360) over the active region (fig. 11C: 360 arranged over AF/ACT);
recessing the active region to form source/drain trenches (¶ 0101 & fig. 11D: AF/ACT recessed to form regions 350);
forming a first source/drain layer (¶ 0083: 384 and/or 386) over the active region in the source/drain trenches (fig. 11E: 384/386 formed over ACT in region 350) from a first precursor (¶ 0104: 384/386 formed from at least one precursor gas); and
forming a second source/drain layer (¶ 0083: 386 and/or 388) over the first source/drain layer (fig. 11E: 386/388 formed over 384/386) from a second precursor (¶ 0104: 386/386 formed from at least on precursor gas).
Kim further teaches the second source/drain layer has different germanium concentration from the first source/drain layer (¶ 0083).
Kim does not teach the second precursor being different from the first precursor.
Lin teaches using different precursors for forming first and second source/drain layers (¶ 0053: at least precursor conditions of a second epitaxial growth different from precursor conditions of a first epitaxial growth).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Kim with a second precursor different from a first precursor, as a means to optimize the shape of the first and/or second source/drain layers (Lin, ¶ 0053), allowing for improved gate-to-source/drain capacitance (Lin, ¶ 0070).
Regarding claim 16, Kim in view of Lin teaches the method of claim 14, wherein the first source/drain layer includes crystalline silicon (Kim, ¶ 0083: 384/386 comprises silicon-containing epitaxial material, and is therefore crystalline), and the first precursor is silane (SiH4) (Kim, ¶ 0104).
Regarding claim 20, Kim in view of Lin teaches the method of claim 14, further comprising:
forming a silicide layer (Kim, ¶ 0088: 430) over and directly contacting the first source/drain layer, and over and directly contacting the second source/drain layer (Kim, fig. 10B: 430 over and directly contacts 384/386 and 386/388).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin as applied to claim 14 above, and further in view of Xie et al. (PG Pub. No. US 2018/0294348 A1).
Regarding claim 15, Kim in view of Lin teaches the method of claim 14, wherein the second source/drain layer includes crystalline silicon (Kim, ¶ 0084: 386/388 comprises silicon-containing epitaxial material, and is therefore crystalline) and a second precursor (Lin, ¶ 0053).
Kim in view of Lin does not teach wherein the second precursor is dichlorosilane (SiH2Cl2).
Xie teaches a method including forming a source/drain layer including crystalline silicon with a dichlorosilane (SiH2Cl2) precursor (¶ 0035: silicon-containing material epitaxially grown with dichlorosilane).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second precursor of Kim in view of Lin with dichlorosilane, as a means to form the second source/drain layer in a conformal manner (Xie, ¶ 0035).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin as applied to claim 14 above, and further in view of Yoo.
Regarding claim 18, Kim in view of Lin teaches the method of claim 14, including forming of a first source/drain layer (Kim, 384/386).
Kim in view of Lin does not teach forming the first source/drain layer includes promoting a growth rate of a <100> facet of the first source/drain layer as compared to a <110> facet of the first source/drain layer.
Yoo teaches forming a source/drain layer resembling a heptagon (¶ 0075, fig. 7: 210/210 include hexagonal cross-section) by promoting growth of the source/drain layer along <100> facets (¶ 0075).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first source/drain layer formation of Kim in view of Lin to include promoting a growth rate of a <100> facet as compared to a <110> facet, as a means to provide a heptagonal shape of the source/drain layer, resisting short channel effect and provide higher drive current at low voltages (Yoo, ¶ 0004).
In addition, configuring the heptagonal semiconductor layer to further include two substantially vertical sidewalls would involve nothing more than routine skill. The Examiner asserts that a person of ordinary skill in the art would recognize that heptagonal semiconductor layers could be provided with or without two substantially vertical sidewalls, which would amount to nothing more that a change in shape. Absent persuasive evidence that the particular shape of the claimed first source/drain layer is significant, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin as applied to claim 14 above, and further in view of Chang et al. (PG Pub. No. US 2018/0138282 A1).
Regarding claim 19, Kim in view of Lin teaches the method of claim 14, including forming of a second source/drain layer (Kim, 386/388).
Kim in view of Lin does not teach forming the second source/drain layer includes suppressing a growth rate of a <100> facet of the second source/drain layer relative to a <110> facet of the second source/drain layer.
Chang teaches a method including forming a source/drain layer by suppressing a growth rate of a <100> facet of the second source/drain layer relative to a <110> facet of the second source/drain layer (¶ 0050 & fig. 2D: 124 grown by suppressing <100> facet relative to <110> facet, forming epitaxial shape similar to that of Kim and/or Lin).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second source/drain layer formation of Kim in view of Lin with the selective facet growth of Chang, as a means to provide lower source/drain contact resistances (Chang, ¶ 0062)
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten or amended to overcome the formal objections set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“performing a first epitaxial growth process to form a first epitaxial layer in the source/drain trench, the first epitaxial layer comprising a profile that resembles a heptagon comprises a substantially heptagonal shape in a first cross-sectional view;
performing a second epitaxial growth process to form a second epitaxial layer in the source/drain trench and on the first epitaxial layer, the second epitaxial layer comprising a profile that resembles an octagon comprises a substantially octagonal shape in the first cross-sectional view” as recited in claim 1.
Yoo teaches a method of epitaxially growing a first semiconductor layer (¶ 0040: 210 and/or 220) resembling a heptagon (¶ 0075, fig. 7: 210/210 include hexagonal cross-section), but fails to teach a second epitaxial growth process to form a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising a profile that resembles an octagon shape.
Chang et al. (PG Pub. No. US 2021/0376155 A1) teaches an epitaxial growth process to form a second epitaxial layer (93 or 126) on a first epitaxial layer (91), the second epitaxial layer comprising a profile that resembles an octagon shape (¶ 0108, fig. 24C: second epitaxial material grown with octagonal shape). However, Chang fails to teach the first epitaxial layer comprising a profile that resembles a heptagon.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“the forming of the another source/drain layer includes conducting a first deposition for a first time duration, the forming of the first source/drain layer includes conducting a second deposition for a second time duration, and wherein a ratio of the first time duration to the second time duration is about 5:1 to about 50:1” as recited in claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights