DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Objections
Claims 15 and 20 are objected to because of the following informalities: claims 15 and 20 recite “the method” in line 1 of both claims. However, claims 15 and 20 are dependent on apparatus/product claim which is a semiconductor device and not a method. Claims 15 and 20 should instead recite “the semiconductor device of claim 14” and “the semiconductor device of claim 19,” respectively. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bao et al. US PGPub. 2024/0186393. Regarding claim 14, Bao teaches a semiconductor device (pFET and nFET, fig. 30A), comprising: a channel portion (2702, fig. 30A) [0129]; an interfacial layer (801+810, fig. 30A and 8A) [0069]-[0070] which is disposed on the channel portion (2702) and which includes a first dielectric material (SiO2 [0069] doped with lanthanum (La), yttrium (Y)[0070]; hereinafter called YSiO), the first dielectric material (YSiO) including a rare-earth metal (yttrium (Y) [0070]); a gate dielectric layer (802, fig. 30A) [0068] which is disposed on the interfacial layer (801+810) and which includes a second dielectric material (HfO2, [0072]), the second dielectric material (HfO2) being different from the first dielectric material (YSiO); and a gate electrode (3002, fig. 30A) [0129] disposed on the gate dielectric layer (802) such that the gate electrode (3002) is separated from the channel portion (2702) by the interfacial layer (801+810) and the gate dielectric layer (802) (Bao et al., fig. 8A and 30A).
Regarding claim 19, Bao teaches the semiconductor device as claimed in claim 14, further comprising dipole elements (810, fig. 8A) [0070] present in at least one of the interfacial layer (801) and the gate dielectric layer (802) in a predetermined amount such that the semiconductor device has a predetermined threshold voltage [0070] (Bao et al., fig. 30A, [0070]).
Regarding claim 20, Bao teaches the semiconductor device as claimed in claim 19, wherein the dipole elements include lanthanum (La) [0070], lutetium (Lu), scandium (Sc), yttrium (Y) [0070], thulium (Tm), gadolinium (Gd), aluminum (Al), zinc (Zn), gallium (Ga) [0070], or combinations thereof (Bao et al., [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. US PGPub. 2024/0186393 as applied to claim 14 above, and further in view of Bojarczuk, JR. et al. US PGPub. 2002/0145168. Regarding claim 15, Bao teaches the method as claimed in claim 14, wherein the first dielectric material (SiO2 doped with Y) but the dielectric constant is not known or mentioned and therefore does not teach that the first dielectric material has a dielectric constant that is greater than a dielectric constant of silicon oxide. However, Bojarczuk teaches a semiconductor device (125, fig. 1) [0004] and [0042] comprising an interfacial layer (121, fig. 1) [0030] wherein the first dielectric material (yttrium silicate/Y2Si2O7, [0030], [0040]) in the interfacial layer (121) has a dielectric constant that is greater than a dielectric constant of silicon oxide (Bojarczuk et al., fig. 1, [0030],[0040]). See Lai et al. US PGPub. 2016/0093616 [0015] that shows evidence that the dielectric constant of YSiO is greater than 4 and considered as a high dielectric constant. At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the first dielectric material of Bao with the yttrium silicate/Y2Si2O7, of Bojarczuk because yttrium silicate is well known in the art and such material is art recognized and suitable for the intended purpose of providing a dielectric stack that increases capacitance while reducing leakage current (Bojarczuk et al., [0012]) (see MPEP 2144.07).
Regarding claim 16, Bao does not teach the semiconductor device as claimed in claim 14, wherein the first dielectric material (SiO2 doped with Y) is a rare-earth metal silicate which includes scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or combinations thereof.
However, Bojarczuk teaches a semiconductor device (125, fig. 1) [0004] and [0042] comprising an interfacial layer (121, fig. 1) [0030] comprising a first dielectric material (yttrium silicate/Y2Si2O7, [0030], [0040]) is a rare-earth metal silicate which includes scandium (Sc), yttrium (Y) [0040], lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or combinations thereof (Bojarczuk et al., fig. 1, [0030],[0040]).
At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the first dielectric material of Bao with the yttrium silicate/Y2Si2O7, of Bojarczuk because yttrium silicate is well known in the art and such material is art recognized and suitable for the intended purpose of providing a dielectric stack that increases capacitance while reducing leakage current (Bojarczuk et al., [0012]) (see MPEP 2144.07).
Claims 1-3 and 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. US PGPub. 2024/0186393 in view of Bojarczuk, JR. et al. US PGPub. 2002/0145168. Regarding claim 1, Bao teaches a method for manufacturing a semiconductor device (fig. 8A-30A), comprising: forming a channel portion (702, fig. 8A; 2702, fig. 30A) [0064], [0129] which includes a semiconductor material (Si, [0070]); forming a an interfacial layer (801+810, fig. 8A and 30A) [0069]-[0070] which includes a first dielectric material (SiO2 doped with Y, [0069]-[0070] and which is formed on the channel portion (2702); forming a gate dielectric layer (802, fig. 8A ad 30A) [0068] which includes a second dielectric material (HfO2, [0072]) and which is formed on the interfacial layer (801+810), the second dielectric material (HfO2, [0072]) being different from the first dielectric material (SiO2 doped with Y, [0070]); and forming a gate electrode (3002, fig. 30S) [0129] on the gate dielectric layer (802) such that the gate electrode (3002) is separated from the channel portion (2702) by the interfacial layer (801+810) and the gate dielectric layer (802) (Bao et al., fig. 8A and 30A). But Bao fails to teach sequentially forming a first oxide film and a second oxide film on the channel portion, the first oxide film and the second oxide film being made of different materials, one of the first oxide film and the second oxide film including a rare-earth metal; performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material. However, Bojarczuk teaches a method of manufacturing a semiconductor device (125, fig. 1) [0004] and [0042] comprising: sequentially forming a first oxide film (SiO2 115, fig. 1) and a second oxide film (metal oxide 111, Y2O3 , fig. 1)[0031] on the channel portion (silicon 113), the first oxide film (SiO2) and the second oxide film (Y2O3, [0031]) being made of different materials, one of the first oxide film (SiO2) and the second oxide (Y2O3) film including a rare-earth metal (yttrium, Y, [0031]); performing a treatment (annealing, [0030]) such that the first oxide film (SiO2) and the second oxide film (Y2O3) are formed into an interfacial layer (121, fig. 1) which includes a first dielectric material (yttrium silicate/Y2Si2O7, [0030], [0040]) (Bojarczuk et al., fig. 1). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the interfacial layer/first dielectric material of Bao with the yttrium silicate/Y2Si2O7, of Bojarczuk because yttrium silicate is well known in the art and such material is art recognized and suitable for the intended purpose of providing a dielectric stack that increases capacitance while reducing leakage current (Bojarczuk et al., [0012]) (see MPEP 2144.07). Regarding claim 2, Bao in view of Bojarczuk teaches the method as claimed in claim 1, wherein the rare-earth metal includes scandium (Sc), yttrium (Y) [0031], lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or combinations thereof (Bojarczuk et al., [0031]).
Regarding claim 3, Bao in view of Bojarczuk teaches the method as claimed in claim 1, wherein the first oxide film (115) includes silicon oxide [0030], the second oxide film (111) includes a rare-earth metal oxide (Y2O3, [0031]), and the treatment includes a thermal process [0030] so as to permit the rare-earth metal oxide of the second oxide film (111) to react with the silicon oxide of the first oxide film (115) so as to form the first dielectric material (yttrium silicate/Y2Si2O7, [0030], [0040]) (Bojarczuk et al., fig. 1). Regarding claim 6, Bao in view of Bojarczuk teaches the method as claimed in claim 3, wherein the second oxide film includes yttrium oxide (Y2O3, [0031]), gadolinium oxide, cerium oxide, lanthanum oxide, lutetium oxide, or combinations thereof, and the first dielectric material (121) includes yttrium silicate (yttrium silicate/Y2Si2O7, [0030], [0040]), gadolinium silicate, cerium silicate, lanthanum silicate, lutetium silicate, or combinations thereof (Bojarczuk et al., fig. 1, [0030]-[0031] and [0040]). Regarding claim 7, Bao in view of Bojarczuk teaches the method as claimed in claim 3, wherein the second oxide film (Y2O3, [0031]) has a lattice constant that is an integer multiple of a lattice constant of the semiconductor material (Si/SiGe) (Bojarczuk et al., fig. 1, [0031]). Where the claimed and the prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. Since the composition is the same, the product must necessarily exhibit the properties. MPEP 2112.01. In this case, since the second oxide film (Y2O3, [0031]) is the same as that of the invention (see [0059] of the publication of the instant application), then the second oxide film (Y2O3, [0031]) of Bojarczuk would obviously also have the same property of that of the invention that has a lattice constant that is an integer multiple of a lattice constant of the semiconductor material. Regarding claim 8, Bao in view of Bojarczuk teaches the method as claimed in claim 7, wherein the semiconductor material includes silicon [0070]) (Bao et al., fig. 8A [0070]).
Regarding claim 9, Bao in view of Bojarczuk teaches the method as claimed in claim 1, wherein the first dielectric material (yttrium silicate/Y2Si2O7, [0030], [0040]) has a dielectric constant that is greater than a dielectric constant of silicon oxide (Bojarczuk et al., fig. 1, [0030],[0040]). See Lai et al. US PGPub. 2016/0093616 [0015] that shows evidence that the dielectric constant of YSiO is greater than 4 and considered as a high dielectric constant. Regarding claim 10, Bao teaches a method for manufacturing a semiconductor device (fig. 8A-30A), comprising: forming a channel portion (702, fig. 8A; 2702, fig. 30A) [0064], [0129]; forming an interfacial layer (801, fig. 8A and 30A) [0069]-[0070] which includes a first dielectric material (SiO2, [0069]) and which is formed on the channel portion (2702); forming a gate dielectric layer (802, fig. 8A ad 30A) [0068] which includes a second dielectric material (HfO2, [0072]) and which is formed on the interfacial layer (801+810), the second dielectric material (HfO2, [0072]) being different from the first dielectric material (SiO2 doped with Y); introducing dipole elements (810, fig. 8A) [0070] into at least one of the interfacial layer (801) and the gate dielectric layer (8002) in a predetermined amount such that the semiconductor device (fig. 30A) has a predetermined threshold voltage [0070]; and forming a gate electrode (3002, fig. 30S) [0129] on the gate dielectric layer (802) such that the gate electrode (3002) is separated from the channel portion (2702) by the interfacial layer (801) and the gate dielectric layer (802) (Bao et a., fig. 8A and 30A). But Bao does not teach forming an interfacial layer (801, fig. 8A) [0069] which includes a first dielectric material (SiO2, [0069]) wherein the first dielectric material including a rare-earth metal. However, Bojarczuk teaches a method of manufacturing a semiconductor device (125, fig. 1) [0004] and [0042] comprising: forming an interfacial layer (metal oxide 111, Y2O3, fig. 1)[0031] which includes a first dielectric material (Y2O3, fig. 1)[0031], wherein the first dielectric material (Y2O3) including a rare-earth metal (yttrium Y, [0031]) (Bojarczuk et al., fig. 1). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the interfacial layer/first dielectric material of Bao with the yttrium oxide which is later annealed to form yttrium silicate/Y2Si2O7, of Bojarczuk because yttrium oxide and yttrium silicate is well known in the art and such material is art recognized and suitable for the intended purpose of providing a dielectric stack that increases capacitance while reducing leakage current (Bojarczuk et al., [0012]) (see MPEP 2144.07). Regarding claim 11, Bao in view of Bojarczuk teaches the method as claimed in claim 10, wherein the dipole elements (810) include lanthanum (La) [0070], lutetium (Lu), scandium (Sc), yttrium (Y) [0070], thulium (Tm), gadolinium (Gd), aluminum (Al), zinc (Zn), gallium (Ga)[0070], or combinations thereof (Bao et al., fig. 8A, [0070]).
Regarding claim 12, Bao in view of Bojarczuk teaches the method as claimed in claim 10, wherein formation of the interfacial layer (121, fig. 1; yttrium silicate/Y2Si2O7, [0030], [0040]) includes: sequentially forming a first oxide film (SiO2 115, fig. 1) and a second oxide film (metal oxide 111, Y2O3 , fig. 1)[0031] on the channel portion (silicon 113), the first oxide film (SiO2) and the second oxide film (Y2O3, [0031]) being made of different materials, one of the first oxide film (SiO2) and the second oxide (Y2O3) film including a rare-earth metal (yttrium, Y, [0031]); performing a treatment (annealing, [0030]) such that the first oxide film (SiO2) and the second oxide film (Y2O3) are formed into an interfacial layer (121, fig. 1; yttrium silicate/Y2Si2O7, [0030], [0040]) (Bojarczuk et al., fig. 1). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the interfacial layer/first dielectric material of Bao with the yttrium silicate/Y2Si2O7, of Bojarczuk because yttrium silicate is well known in the art and such material is art recognized and suitable for the intended purpose of providing a dielectric stack that increases capacitance while reducing leakage current (Bojarczuk et al., [0012]) (see MPEP 2144.07). Regarding claim 13, Bao in view of Bojarczuk teaches the method as claimed in claim 12, wherein the first oxide film (115) includes silicon oxide (fig. 1), the second oxide film (111) is made of a rare-earth metal oxide which includes scandium (Sc), yttrium (Y) yttrium oxide (Y2O3, [0031]), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or combinations thereof, and the first dielectric material (121) is a rare-earth metal silicate which includes scandium (Sc), yttrium (Y) (yttrium silicate/Y2Si2O7, [0030], [0040]), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or combinations thereof (Bojarczuk et al., [0030]-[0031] and [0040])
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. US PGPub. 2024/0186393 in view of Bojarczuk, JR. et al. US PGPub. 2002/0145168 as applied to claim 2 above, and further in view of Galatage et al. US PGPub. 2024/0204103. Regarding claim 4, Bao in view of Bojarczuk does not teach the method as claimed in claim 2, further comprising: after formation of the second oxide film (111) and before the thermal process, forming a cap layer to cover the second oxide film (111), and removing the cap layer after the thermal process. However, Galatage teaches a method of manufacturing a semiconductor device (1100, fig. 11) comprising: after formation of the second oxide film (step 1108, next dipole layer, fig. 11) and before the thermal process (anneal step 1112, fig. 1), forming a cap layer (step 1110, fig. 11) to cover the second oxide film (next dipole layer), and removing the cap layer (step 1114, fig. 11) after the thermal process (anneal step 1112) (Galatage et al., fig. 11). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the annealing of Bao and Bojarczuk by adding the cap layer and removing it in the sequence as taught by Galatage because such process is well known in the art and such process is art recognized and suitable for the intended purpose of providing a hermetic sealant and/or oxygen diffusion barrier (Galatage et al., [0069]) (see MPEP 2144.07). Regarding claim 5, Bao in view of Bojarczuk and Galatage teaches the method as claimed in claim 4, wherein the cap layer includes silicon (amorphous silicon [0069]) (Galatage et al., [0069]).
Allowable Subject Matter
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device comprising “a barrier layer which is disposed between the interfacial layer and the gate dielectric layer, and which includes a barrier material, the barrier material having a conduction band edge energy that is greater than a conduction band edge energy of each of the first dielectric material and the second dielectric material, and a valance band edge energy that is lower than a valance band edge energy of each of the first dielectric material and the second dielectric material” as recited in claim 17 in combination with the rest of the limitations of claim 14.
Claim 18 is also objected to as allowable for further limiting and depending upon allowable claim 17. Conclusion
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892