DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Omata et al (US Publication 20240144882) in view of Toyotaka et al (US Publication 20210319764).
Regarding claim 8, Omata teaches a display apparatus comprising:
a substrate comprising a display area and a peripheral area adjacent to the display area (Fig. 5, SUB with R1 adjacent to R2, para 54);
a first transistor in the display area (Fig. 38, DRT in R1), and comprising a first semiconductor pattern comprising a first terminal and a second terminal (Fig. 38, DRT with terminals SE and DE) and a first electrode pattern overlapping the first semiconductor pattern (Fig. 38, G overlapping DRT and AE);
a second transistor electrically connected to the first electrode pattern of the first transistor and a data line (Fig. 28, SST electrically connected to electrode pattern for DRT);
a third transistor electrically connected to the first electrode pattern of the first transistor and a reference voltage line (Fig. 28, RST electrically connected to electrode pattern of DRT and Vrst);
a fourth transistor electrically connected to the first terminal of the first transistor and a driving voltage line (Fig. 28, BCT electrically connected to first terminal of DRT and Vsig, para 106 and 109);
a storage capacitor comprising a first capacitor electrode electrically connected to the first electrode pattern of the first transistor (Fig. 38, Cs electrode AE electrically connected to G of DRT, para 384), and a third capacitor electrode electrically connected to the second terminal of the first transistor and overlapping the first electrode pattern of the first transistor (Fig. 38, SC electrically connected to DE and overlapping G); and
a hold capacitor comprising a second capacitor electrode and the third capacitor electrode (Fig. 38, Cad with OE and SC),
wherein the third capacitor electrode is on an insulating layer covering a driving semiconductor pattern (Fig. 38, SC on PL);
at least a channel region of the first transistor overlaps the storage capacitor and the hold capacitor in a plan view (Fig. 38, the channel region of DRT spans the continuous length of SC, claims 8 and 14, thus the channel region of DRT overlaps with Cad and Cs).
Omata does not specifically teach a driving transistor in the peripheral area, and comprising a driving semiconductor pattern and a driving gate electrode overlapping the driving semiconductor pattern.
Toyotaka teaches a driving transistor in the peripheral area, and comprising a driving semiconductor pattern and a driving gate electrode overlapping the driving semiconductor pattern (Fig. 15A, 4011 in 221a with 4017 overlapping 4011).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Omata to include a driving transistor in the peripheral area as taught by Toyotaka in order to increase the active display area, improve image quality, and reduce the bezel size of the device.
Regarding claim 9, Omata as modified teaches the limitations of claim 8 upon which claim 9 depends.
Omata teaches wherein an area where the first semiconductor pattern and the first electrode pattern overlap each other is inside of the third capacitor electrode in a plan view (Fig. 38, DRT and G on SC (overlapping as stated in the instant application para 113)).
Regarding claim 10, Omata as modified teaches the limitations of claim 8 upon which claim 10 depends.
Omata teaches wherein the driving voltage line comprises a first voltage line extending in a first direction and a second voltage line extending in a second direction intersecting the first direction (Fig. 33, Sla extending in the y direction, Pla extending in x direction, para 302 and 382), and the second voltage line and the second capacitor electrode are integral (OE layer connected to PSH and thus Pla).
Regarding claim 11, Omata as modified teaches the limitations of claim 8 upon which claim 11 depends.
Omata teaches wherein the driving gate electrode, the first capacitor electrode, and the second capacitor electrode are on a same layer (Fig. 38, G, AE, and OE on PL).
Regarding claim 12, Omata as modified teaches the limitations of claim 11 upon which claim 12 depends.
Omata teaches the third capacitor electrode is on the first capacitor electrode and the second capacitor electrode (Fig. 38, SC on OE and AE), and
the third capacitor electrode overlaps the first capacitor electrode and the second capacitor electrode (Fig. 38, SC overlaps OE and AE).
Regarding claim 13, Omata as modified teaches the limitations of claim 8 upon which claim 13 depends.
Omata teaches a connection electrode that electrically connects the second terminal of the first transistor to the third capacitor electrode (Fig. 38, portion of DE connecting bulk of DE to SC).
Regarding claim 14, Omata as modified teaches the limitations of claim 13 upon which claim 14 depends.
Omata teaches wherein the connection electrode overlaps the first electrode pattern (Fig. 38, portion of DE connecting bulk of DE to SC overlaps G).
Regarding claim 18, Omata as modified teaches the limitations of claim 8 upon which claim 18 depends.
Omata does not specifically teach wherein the driving semiconductor pattern comprises a silicon semiconductor material, and the first semiconductor pattern comprises an oxide semiconductor material.
Toyotaka teaches wherein the driving semiconductor pattern comprises a silicon semiconductor material, and the first semiconductor pattern comprises an oxide semiconductor material (para 87, SI and OS transistors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Omata as modified to include the driving semiconductor pattern / first semiconductor layer comprising silicon semiconductor material and the first semiconductor pattern / second semiconductor layer comprising oxide semiconductor material as taught by Toyotaka in order to provide high-speed reliable driving capabilities (SI) with the extremely low leakage current of OS transistors and optimize display power consumption and image quality.
Regarding claim 19, Omata as modified teaches the limitations of claim 8 upon which claim 19 depends.
Omata does not specifically teach wherein one or more insulating layers comprising an insulating material are between the driving semiconductor pattern and the substrate.
Toyotaka teaches wherein one or more insulating layers comprising an insulating material are between the driving semiconductor pattern and the substrate (Fig. 15A, 4011 on 4102, para 211).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Omata as modified to include the insulating material layer as taught by Toyotaka in order to provide a moisture/oxygen barrier, protection against corrosion, and improve the lifespan and performance of the device.
Regarding claim 20, Omata as modified teaches the limitations of claim 8 upon which claim 20 depends.
Omata teaches wherein the second capacitor electrode is electrically connected to the reference voltage line (Fig. 2, OE of Cad electrically connected to Vrst).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Omata et al (US Publication 20240144882) in view of Toyotaka et al (US Publication 20210319764) further in view of Okamoto et al (US Publication 20240321205).
Regarding claims 15-17, Omata as modified teaches the limitations of claims 8 and 13 upon which claim 14 and 15 depend.
Omata teaches:
[claim 16] an organic light-emitting diode comprising a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode (para 199, PE, CE, ORG).
Omata does not specifically teach:
[claim 15] a fifth transistor electrically connected between a first initialization voltage line and the second terminal of the first transistor.
[claim 16] a sixth transistor electrically connected between the second terminal of the first transistor and the organic light-emitting diode.
[claim 17] a seventh transistor electrically connected between the organic light-emitting diode and a second initialization voltage line.
Okamoto teaches:
[claim 15] a fifth transistor electrically connected between a first initialization voltage line and the second terminal of the first transistor.
[claim 16] a sixth transistor electrically connected between the second terminal of the first transistor and the organic light-emitting diode.
[claim 17] a seventh transistor electrically connected between the organic light-emitting diode and a second initialization voltage line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Omata as modified to include the fifth, sixth, and seventh transistors as taught by Toyotaka in order to further optimize and improve the operability and reliability of the device.
Allowable Subject Matter
Claims 1-7 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art including Omata, Toyotaka, and Okamoto does not teach or render obvious "a first conductive layer on the first semiconductor layer, and comprising a first capacitor electrode and a second capacitor electrode; in the display area; a second conductive layer on the first conductive layer, and comprising a third capacitor electrode overlapping the first capacitor electrode and the second capacitor electrode; a second semiconductor layer on the second conductive layer, and comprising a first semiconductor pattern overlapping the third capacitor electrode" and in the combination as claimed.
Claims 2-7 further limit allowable claim 1 therefore are allowable for the same reasons as above.
Response to Arguments
Applicant's arguments filed 13 August 2026 have been fully considered but they are not persuasive.
Regarding claim 8, applicant argues that the cited art does not disclose "at least a channel region of the first transistor overlaps the storage capacitor and the hold capacitor in a plan view". As stated in claims 8 and 14 of Omata "both the channel of the drive transistor and a channel of the output switch are formed of the semiconductor layer continuously". This would imply that the DRT channel region is continuous along the length of SC.
Applicant also argues that the Omata reference relies on SC for the third capacitor electrode of the storage capacitor and the hold capacitor. Applicant states that this SC is a semiconductor layer and also contains the channel region of transistor DRT arguing that the channel region would need to be doped differently than the surrounding portions that make the source and drain electrodes to for a functional TFT. Applicant states that the portions of SC functioning as the capacitor electrodes must be heavily doped to remain in a conductive state while the portion of SC functioning as the channel region of DRT must be undoped/lightly doped so that current flow can be modulated by the gate voltage. Applicant argues that as these are mutually exclusive functions and physical characteristics the channel region of DRT cannot overlap the capacitor electrodes in a plan view.
MPEP 716.001(c) II states:
II. ARGUMENTS BY APPLICANT CANNOT TAKE THE PLACE OF EVIDENCE
Arguments presented by the applicant cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965) and In re De Blauwe, 736 F.2d 699, 705, 222 USPQ 191, 196 (Fed. Cir. 1984). Examples of statements which are not evidence and which must be supported by an appropriate affidavit or declaration include statements regarding unexpected results, commercial success, solution of a long-felt need, inoperability of the prior art, invention before the date of the reference, and allegations that the author(s) of the prior art derived the disclosed subject matter from the inventor or at least one joint inventor.
The Omata reference channel region for the driving transistor and output switch are formed of the semiconductor layer continuously and the same semiconductor layer is an electrode for the hold and storage capacitors. It appears that Applicant is attempting to argue that this layer would be inoperative as a channel (and thus relate to the MPEP section described above that would require further evidence), though even with different doping it still would seemingly allow current flow. As shown in Omata Fig. Fig. 38, the channel region of DRT spans the continuous length of SC thus the channel region of DRT overlaps with Cad and Cs.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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