DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10, 15, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being clearly anticipated by Kim; Hyo-Jin et al. (US 2023/0095830; hereinafter Kim).
Regarding claim 10, Kim discloses a semiconductor structure comprising:
an upper source/drain contact (AC2; Figs 4D,4A; ¶ [0049]) disposed on an upper epitaxial source/drain (SD2; Fig 4D,4A; ¶ [0047]);
a lower source/drain contact (AC1; Fig 4D,4A; ¶ [0041]) disposed on a lower epitaxial source/drain (SD1; Fig 4D,4A; ¶ [0039]); and
a source/drain via (UVI1; Fig 4D; ¶ [0095]) connected to the upper source/drain contact and the lower source/drain contact (Fig 4D; ¶ [0095]), wherein the source/drain via is disposed on the upper source/drain contact (Fig 4D; ¶ [0095]), the source/drain via extends below the upper source/drain contact (Fig 4D), and
the source/drain via includes ruthenium and aluminum (one or more of ruthenium and aluminum are disclosed as materials for various of conductive metal interconnects { including source/drain contact AC1; ¶ [0042]); vias VI; ¶ [0081]; wiring lines MI1 to MI4, and gate contact CG; ¶ [0087-88]}; and UVI1 may be formed concurrently with CG and MI1 to MI4, therefore comprised of the same material; ¶ [0143]).
Regarding claim 15, Kim discloses the semiconductor structure of claim 10, further comprising a gate (GE; Figs 4A,4B; ¶ [0051-54], wherein the upper epitaxial source/drain (SD2; Figs 4A,4D) and the lower epitaxial source/drain (SD1; Figs 4A,4D) form an epitaxial source/drain stack disposed adjacent to the gate, wherein the upper epitaxial source/drain and the lower epitaxial source/drain are on a same side of the gate (as shown in Figs 4A,4D).
Regarding claim 17, Kim discloses a device comprising:
a transistor stack having a first transistor (comprising AR2; Figs 4A,4D; ¶ [0033]) over a second transistor (comprising AR1; Figs 4A,4D; ¶ [0033]), wherein:
the first transistor includes a first channel layer (CH2; Fig 4A; ¶ [0045]), a first gate (the portion of GE on CH2; Fig 4A; ¶ [0051-54]), and first source/drains (SD2; Fig 4D,4A; ¶ [0047]), wherein the first gate is disposed on the first channel layer and the first channel layer is disposed between the first source/drains (as shown in Fig 4A), and
the second transistor includes a second channel layer (CH1; Fig 4A; ¶ [0038]), a second gate (the portion of GE on CH1; Fig 4A; ¶ [0051-54]), and second source/drains (SD1; Fig 4D,4A; ¶ [0039]), wherein the second gate is disposed on the second channel layer and the second channel layer is disposed between the second source/drains (as shown in Fig 4A),
a first source/drain contact (AC2; Figs 4D,4A; ¶ [0049]) and a second source/drain contact (AC1; Figs 4D,4A; ¶ [0041]), wherein the first source/drain contact is disposed on one of the first source/drains and the second source/drain contact is disposed on one of the second source/drains; and
a source/drain via (UVI1; Fig 4D; ¶ [0095,0097]) disposed on the first source/drain contact and the second source/drain contact (Fig 4D), wherein the source/drain via is connected to the first source/drain contact and the second source/drain contact (¶ [0095,0097]) and the source/drain via includes ruthenium and aluminum (one or more of ruthenium and aluminum are disclosed as materials for various of conductive metal interconnects {including source/drain contact AC1; ¶ [0042]); vias VI; ¶ [0081]; wiring lines MI1 to MI4, and gate contact CG; ¶ [0087-88]}; and UVI1 may be formed concurrently with CG and MI1 to MI4, therefore comprised of the same material; ¶ [0143]).
Regarding claim 20, Kim discloses the device of claim 17, wherein the second source/drain contact (AC1; Figs 4D,4A) wraps a bottom end of the source/drain via (UVI1; Fig 4D). (Via UVI1 penetrates AC1 {¶ [0097]}; AC1 therefore wraps a bottom end of UVI1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim; Hyo-Jin et al. (US 2023/0095830; hereinafter Kim) in view of Son; Gilhwan et al. (US 2024/0194768; hereinafter Son).
Regarding claim 12, Kim discloses the semiconductor structure of claim 10, but does not disclose wherein the source/drain via (UVI1; Fig 4D) includes a ruthenium aluminide plug.
In the same field of endeavor, Son discloses a semiconductor structure comprising a source/drain contact plug which may include an alloy of ruthenium and aluminum (142; Fig 3; ¶ [0040]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the ruthenium and aluminum included in the source/drain via of Kim may comprise ruthenium aluminide (an alloy of ruthenium and aluminum). One may have been motivated to come to this conclusion, with a reasonable expectation of success due to Son’s disclosure of an alloy of ruthenium and aluminum used in the structure similar to that of Kim (contact/via), and because ruthenium aluminide is a known alloy in the art.
Claims 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim; Hyo-Jin et al. (US 2023/0095830; hereinafter Kim) in view of Cho; Kyunghee et al. (US 2024/0321886; hereinafter Cho).
Regarding claim 14, Kim discloses the semiconductor structure of claim 10, but does not disclose wherein the source/drain via (UVI1; Fig 4D) extends below a top of the lower epitaxial source/drain (SD1; Fig 4D).
In the same field of endeavor, Cho discloses a related semiconductor structure comprising upper and lower source/drain contacts (CA and bCA respectively; Fig 10E; ¶ [0089]) connected by a source/drain via (VA; Fig 10E; ¶ [0089]), wherein the source/drain via extends below a top of a lower epitaxial source/drain (SDD/SDDa; Fig 10E; ¶ [0089]), the lower source/drain contact being below the lower epitaxial source/drain. It would have been obvious to a person having ordinary skill in the art to have combined the structures of Kim and Cho such that the source/drain via connects or extends to a portion of the lower source/drain contact at a point below at least a top of a lower epitaxial source/drain. One may have been motivated to do this in order to accommodate a particular circuit design, performance or manufacturing requirement as may be met by modification of Kim’s structure. One would have had a reasonable expectation of success due to the similar structures of Kim and Cho in the similar endeavors, and because a variety of source/drain contact positional configurations are known in the art.
Regarding claim 19, Kim discloses the device of claim 17, but does not disclose wherein the source/drain via (UVI1; Fig 4D) spans a distance between a bottom of the one of the first source/drains (SD2; Fig 4D) and a top of the one of the second source/drains (SD1; Fig 4D).
In the same field of endeavor, Cho discloses a related device comprising first and second source/drain contacts (CA and bCA respectively; Fig 10E; ¶ [0089]) connected by a source/drain via (VA; Fig 10E; ¶ [0089]), wherein the source/drain via spans a distance between a bottom of a first source/drain (SDU/SDUa; Fig 10E; ¶ [0089]), and a top of a second source/drain SDD/SDDa; Fig 10E; ¶ [0089]), the second source/drain contact being below the second source/drain. It would have been obvious to a person having ordinary skill in the art to have combined the structures of Kim and Cho such that the source/drain via spans a distance between a bottom of the one of the first source/drains and a top of the one of the second source/drains. One may have been motivated to do this in order to accommodate a particular circuit design, performance or manufacturing requirement as may be met by modification of Kim’s structure. One would have had a reasonable expectation of success due to the similar structures of Kim and Cho in the similar endeavors, and because a variety of source/drain contact positional configurations are known in the art.
Allowable Subject Matter
Claims 1-9 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a lower source/drain contact opening that exposes a lower epitaxial source/drain and the source/drain via; and forming a lower source/drain contact in the lower source/drain contact opening, wherein the source/drain via connects the upper source/drain contact and the lower source/drain contact.”
Claims 11, 13, 16, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the source/drain via includes a ruthenium plug wrapped by an aluminum liner.”
Regarding claim 13, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the source/drain via includes a ruthenium plug wrapped by a ruthenium aluminide liner”.
Regarding claim 16, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the source/drain via connects the upper source/drain contact and the lower source/drain contact {claim 1}) and “wherein the upper epitaxial source/drain is a portion of a first epitaxial source/drain stack, the lower epitaxial source/drain is a portion of a second epitaxial source/drain stack, and the gate is disposed between the first epitaxial source/drain stack and the second epitaxial source/drain stack”.
Regarding claim 18, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the source/drain via includes a ruthenium plug wrapped by an aluminum liner”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xie; Ruilong et al. (US 20240170532; the prior art discloses a shared source/drain contact for upper and lower source/drains);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights