DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the tapered openings must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 12-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. '242 (US 20190131242 A1), Chang et al. (US 20230069737 A1), and McElhinney et al. (US 20230096835 A1).
Regarding claim 1, Lee et al. ‘242 teaches semiconductor structure, comprising:
A first substrate (as seen in attached Fig. 9) having a first side (as seen in attached Fig. 9) and a second side (as seen in attached Fig. 9) opposite to the first side (as seen in attached Fig. 9), wherein the first side includes a recess recessed from the first side [as seen in attached Fig. 9, ¶0008];
A first semiconductor die (121) arranged in the recess and bonded to the first side of the first substrate [as seen in attached Fig. 9, ¶0008];
A second semiconductor die (122) bonded to the second side of the first substrate [as seen in attached Fig. 9, ¶0008];
A second substrate (as seen in attached Fig. 9) electrically bonded to the first side of the first substrate [as seen in attached Fig. 9, ¶0009], wherein the second substrate has a first side and a second side opposite to the first side;
A plurality of conductive vias (140) positioned along the second substrate and extending through the second substrate [as seen in attached Fig. 9, ¶0068], wherein the;
A passivation layer (151) positioned on the second substrate [as seen in attached Fig. 9, ¶0008]; and
plurality of barrier layers (160) positioned on the second substrate and in the passivation layer (151) [as seen in attached Fig. 9, ¶¶0067 and 0090, barrier layer is underbump metal layer in Lee et al. ‘242 as it provides the same function of better connection reliability];
Lee et al. ‘242 doesn’t teach the conductive vias extending from one side of the substrate through to the other and the plurality of openings to expose portions of the first side.
Chang et al. teaches conductive vias (280) extended through the second substrate (200) from the first side of the second substate to the second side thereof, such that each of the conductive vias has a first end coplanar with the first side of the second substrate and a second end coplanar with the second side of the second substrate [as seen in attached Fig. 2G, ¶0022];
wherein the passivation layer (340, specifically layer 290 ) has a plurality of openings formed therethrough to expose portions of the first side of the second substate (200) and the first ends of the conductive vias at the first side of the second substrate;
wherein the barrier layers (230) are coupled on the first side of the second substate within the openings to cover the first ends of the conductive vias respectively for preventing the conductive vias from corrosion.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to combine the passivation and conductive vias as taught by Chang et al. with the semiconductor package of Lee et al. ‘242 because it would allow for direct connection with the protection desired for the semiconductor package.
Lee et al. ‘242 in view of Chang et al. doesn’t teach a thickness of the passivation layer is greater than a thickness of each of the barrier layers
McElhinney et al. teaches a thickness of the passivation layer (2402) is greater than a thickness of each of the barrier layers (2504) [Figs. 24-26, ¶0075, barrier layer thickness is approximately 3 μm and Fig. 25 showing the thickness of the passivation layer having a greater thickness];
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to combine McElhinney et al. with Lee et al. ‘242 in view of Chang et al. as they both showcase structures for packaging semiconductor dies and interconnects between them. It would have been obvious to include the passivation layer having a greater thickness than the barrier layer as it would be ideal to have the passivation layer being thicker as it would allow for improvement of efficiency and having a smaller barrier layer thickness would allow for the prevention of interdiffusion.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee '242, Lee et al. '557 (US 20210043557 A1), and Moon et al. (US 7229918 B2).
Regarding claim 2, Lee et al. ‘242 in view of Chang et al. and McElhinney et al., here after modified Lee ‘242, teaches the semiconductor structure of claim 1.
Modified Lee ‘242 doesn’t teach the rest of the claimed structure of the conductive via.
Lee et al. ‘557 teaches a conductive via comprising:
Two isolation layers (153) (lining layer, has the same insulating materials) conformally formed on two sidewalls of the via opening [Fig. 1D, ¶0117, formed on the sidewalls and bottoms of the blind holes];
an adhesive layer (154) conformally formed, wherein the adhesive layer has a U-shaped cross-sectional profile and is formed of titanium, tantalum, titanium tungsten, or manganese nitride [Fig. 1F, ¶0117, adhesion layer comprising titanium or titanium nitride];
a seed layer (155) conformally formed on the adhesive layer (154), wherein the seed layer has a U-shaped cross-sectional profile and is formed of copper or ruthenium [Fig. 1F, ¶0117, seed layer made of copper]; and
a filler layer (156, copper layer) formed on the seed layer (155) and completely fill the via opening, wherein the filler layer is copper [Fig. 1F, ¶¶0117-0118, filled the via with copper layer on seed layer].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement the structure of the via from Lee et al. ‘557 into Lee et al. ‘242 because Lee et al. ‘242 discloses via structures through the second substrate and Lee et al. ‘557 disclose a conductive via structure which would help with preventing short circuiting with the isolation layer, a seed layer that helps with filling the opening of a via so there aren’t any gaps, adhesion layer to help with attaching the seed layer to a via, and the filler layer made out of copper to help with increased conduction.
Modified Lee ‘242 and Lee et al. ‘557 doesn’t teach a via barrier layer conformally formed on the isolation layer IL (lining layer) and on the bottom surface of the via opening, wherein the via barrier layer has a U-shaped cross-sectional profile and is formed of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bilayer; and the adhesion layer conformally formed on the barrier layer.
Moon teaches a via barrier layer (406) conformally formed on the isolation layer IL (lining layer, Lee et al. ‘557) and on the bottom surface of the via opening [col. 7 lines 8-26, formed over a material layer with vias and conductive lines], wherein the via barrier layer has a U-shaped cross-sectional profile and is formed of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bilayer [Fig. 9, col. 8 lines 12-24, the layers are made of tantalum, tantalum nitride, titanium, or titanium nitride]; and the adhesion layer (414) conformally formed on the barrier layer [Fig. 9, col. 8 lines 12-24, the layers are made of tantalum, tantalum nitride, titanium, or titanium nitride and adhesion layer as claimed can be made out of titanium or tantalum which would provide the same structure].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the barrier and adhesion layer as described by Moon in Lee et al. ‘242 in further view of Lee et al. ‘557 as the structures described are in relation to vias and the implementation of a barrier layer along with an adhesion layer would be improved diffusion prevention and increased oxidation resistance as described by Moon in Col. 7 Lines 50-60.
Regarding claim 3, modified Lee ‘242, Lee et al. ‘557, and Moon teaches the semiconductor structure of claim 2, wherein the two isolation layers (153) are formed of silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate [¶0117, silicon oxide, Lee et al. ‘557].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Lee et al. ‘557 (US 20210043557 A1), Moon (US 7229918 B2), and Shih (US 20220037287 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Modified Lee ‘242 in further view of Lee et al. ‘557 and Moon teaches the semiconductor structure of claim 3.
Modified Lee et al. ‘242 in further view of Lee et al. ‘557 and Moon doesn’t teach the semiconductor structure of claim 3, wherein the two isolation layers have a thickness between about 50 nm and about 200 nm.
Shih teaches the semiconductor structure of claim 3, wherein the two isolation layers have a thickness between about 50 nm and about 200 nm [¶0048, range from 10 nm to 200nm].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to utilize a thickness between about 50 nm and about 200 nm as this range would allow the ideal thickness for the isolation layer depending on the needs of the semiconductor structure.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Lee et al. ‘557 (US 20210043557 A1), Moon (US 7229918 B2), and Lu (US 20210020579 A1).
Regarding claim 5, modified Lee ‘242 in further view of Lee et al. ‘557 and Moon teaches the semiconductor structure of claim 2.
Modified Lee ‘242 in further view of Lee et al. ‘557 and Moon doesn’t teach the semiconductor structure of claim 2, wherein the two isolation layers are formed of parylene, epoxy, or poly(p-xylene).
Lu et al. teaches the semiconductor structure of claim 2, wherein the two isolation layers (17a and 17b) are formed of parylene, epoxy, or poly(p-xylene) [¶0050, isolation layers made from epoxy or epoxy-based material].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement the epoxy material from Lu into Lee et al. ‘242 in further view of Lee et al. ‘557 and Moon because both structures describe a semiconductor structure that includes isolation layers, seed layer, and filling layer (metal layer). The structure of the semiconductor from Lu has the same capabilities of connection and between electronic components (chips/dies) as the structure described by Lee et al. ‘242 in further view of Lee and Lu and Moon, allowing for a person with ordinary skill in the art to combine the art to have the isolation layers be made from epoxy as it is an insulating material that would help with short circuit prevention.
Regarding claim 6, modified Lee ‘242 in further view of Lee et al. ‘557, Moon, and Lu teaches the semiconductor structure of claim 5.
Modified Lee ‘242 in further view of Lee et al. ‘557, Moon, and Lu further teaches the semiconductor structure of claim 5, wherein the two isolation layers have a thickness between about 1 μm and about 5 μm [¶0050, thickness of isolation layers about 2 μm and about 5 μm].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement the thickness of the isolation layer as it is seen to be within a range that would be ideal for the structure.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Lee et al. ‘557, Moon, and Wei et al. (US 20220102164 A1).
Regarding claim 7, modified Lee ‘242 in further view of Lee et al. ‘557 and Moon teaches the semiconductor structure of claim 2.
Modified Lee ‘242 in further view of Lee et al. ‘557e and Moon doesn’t teach the adhesive layer having a thickness between about 5 nm and about 50nm.
Wei et al. teaches an adhesive layer has a thickness between about 5nm and about 50 nm [¶0090, adhesive layer range 2nm to 500nm].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement the thickness of the adhesive layer as it is seen to be within a range that would be ideal for the claimed semiconductor structure.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Lee et al. ‘557, Moon, and Bando et al. (US 20230145328 A1).
Regarding claim 8, modified Lee ‘242 in further view of Lee et al. ‘557 and Moon teaches the semiconductor structure of claim 2.
Modified Lee ‘242 in further view of Lee et al. ‘557 and Moon doesn’t teach the thickness of the seed layer to be between about 10nm and about 40nm.
Bando et al. teaches the seed layer thickness to be between about 5nm and about 50nm [¶0038, seed layer thickness range from about 10nm to about 300nm, the titanium layer of the two-layer metal film (described as seed layer) can be seen as a stand-alone seed layer as Bando et al. describes the titanium to help with contractability and help restrain diffusion which are aspects of a seed layer].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement a seed layer thickness within the range presented by Brando et al. as it would be seen as ideal for the semiconductor structure and to maintain a small structure.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. '242 (US 20190131242 A1), Chang et al. (US 20230069737 A1), and McElhinney et al. (US 20230096835 A1).
Regarding claim 12, modified Lee ‘242 teaches the semiconductor structure of claim 1, further comprising a plurality of connectors (500) positioned on the barrier layers (320) respectively, extended through the passivation layer (340), and protruded out of the passivation layer [Fig. 2S, ¶0035, Chang et al.].
Regarding claim 13, modified Lee ‘242 teaches the semiconductor structure of claim 12, wherein each of the connectors (500) has an upper portion extended through the passivation layer (340), completely filled the opening, and disposed on the barrier layer [Fig. 2S, ¶0035, Chang et al.].
Regarding claim 14, modified Lee ‘242 teaches the semiconductor structure of claim 13, wherein each of the connectors (500) further has a lower portion integrally extended from the upper portion (320) and protruded from a plane coplanar with the top surface of the passivation layer (340) and disposed on the first portion of the connector (320) [Fig. 2S, ¶0035, Chang et al.].
Regarding claim 15, modified Lee ‘242 teaches the semiconductor structure of claim 1, wherein the passivation layer (151) is made of polybenzoxazole, polyimide, benzocyclobutene, solder resist film, the like, or a combination thereof [as seen in attached Fig. 9, ¶0090, polyimide resin used for passivation layer, Lee et al. ‘242].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Kao et al. (US 20230026305 A1).
Regarding claim 16, modified Lee ‘242 teaches the semiconductor structure of claim.
Modified Lee ‘242 doesn’t teach the material used for the passivation layer.
Kao et al. teaches the passivation layer is made of silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or a combination thereof [¶0052, silicon nitride].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to implement the use of silicon nitride as a passivation layer in Lee et al. ‘242 as described by Kao et al. because the use of silicon nitride was seen to work well as a passivation layer in a semiconductor device that focuses on interconnection as does Lee et al. ‘242
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over modified Lee ‘242 in further view of Yang (US 20220336388 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 17, modified Lee ‘242 teaches the semiconductor structure of claim 1.
Modified Lee ‘242 doesn’t teach the composition of each of the barrier layers.
Yang teaches each of the barrier layers is made of aluminum fluoride, or andzincoxide, wherein a content of zinc oxide is greater than a content of aluminum fluoride [¶0086, sputtering power ratio is seen to have higher sputtering power for zinc oxide which would lead to greater zinc oxide content than aluminum fluoride].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the semiconductor structure as taught by modified Lee ‘242 with the barrier layer composition as taught by Yang because this would allow for increased electrical properties of the barrier layer [¶0086, Yang].
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. '242 (US 20190131242 A1), Chang et al. (US 20230069737 A1), and McElhinney et al. (US 20230096835 A1).
Regarding claim 18, modified Lee ‘242 teaches the semiconductor structure of claim 1, wherein a sidewall of each of the openings is tapered [Fig. 2A, ¶0014, Chang et al.].
Regarding claim 19, modified Lee ‘242 teaches the semiconductor structure of claim 12, wherein each of the connectors is a solder joint [Fig. 9, ¶0093, Lee et al. ‘242].
Regarding claim 20, modified Lee ‘242 teaches the semiconductor structure of claim 19, wherein the solder joint is made of tin, silver, or copper [¶0093, solder may include tin-silver or copper, Lee et al. ‘242].
Response to Arguments
Applicant’s arguments, see pages 6-8 in amendment, filed 04/16/2026, with respect to the rejection(s) of claim(s) 1 and 17 under Lee et al. '242 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al. '242 in view of Chang et al. and McElhinney et al. and in further view of Yang et al. for claim 17. The applicant’s remarks focused on the formation of the conductive vias claimed in claim 1 which are taught by Chang et al. and the barrier layer composition which is taught by Yang et al. in the rejection for claim 17. Refer to the rejections above.
Applicant's arguments filed on 04/16/2026 in regards to the combination of the prior art used for the rejection have been fully considered but they are not persuasive. McElhinney is used for the thickness of the barrier layer in regards to the passivation layer which would be reasonable to implement in combination with Lee et al. '242 and Chang et al. as stated above. All other aspects of the claims are taught by other references. The amended claims were taken into account and prior art was found to reject those amendments made which were seen to overcome the previous rejection as seen above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOOR MOHAMMAD ISMAIL TAHIR/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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