DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (US 2016/0111537).
With regards to claim 1, figs. 6a and 12 of Tsai discloses a fin field effect transistor (FinFET) device structure (“FinFET”, par [0044]), comprising: a plurality of fin structures 110 above a substrate 102; an isolation structure STI over the substrate 102 and between the fin structures 110; a gate structure 114 formed over the fin structure 110; a source/drain (S/D) structure 122’ over the fin structure 110, wherein the S/D structure 122’ is adjacent to the gate structure 114; a metal silicide layer (“NiSi metal-silicide layer 142”, par [0044]) over the S/D structure 122’, wherein the metal silicide layer 142 is in contact 106 with the isolation structure 106; and a metal layer 144 over the isolation structure 106 and adjacent to the metal silicide layer 142, wherein a bottom surface (bottom of 144) of the metal layer 144 is substantially level with a bottom surface (bottom of 142) of the metal silicide layer 142.
With regards to claim 2, figs. 6a and 12 of Tsai discloses that the S/D structure 122’ comprises a doped region (“B-doped “, par [0021]) at an outer portion of the S/D structure 122’, and the doped region comprises gallium (Ga) or boron (B) (“B-doped “, par [0021]).
With regard to claim 8, figs. 6a and 12 of Tsai discloses a fin field effect transistor (FinFET) device structure (“FinFET”, par [0044]), comprising: a fin structure 110 over a substrate 102; a gate structure 114 formed over the fin structure 110; a gate spacer layer 116 on opposite sidewall surfaces of the gate structure 114; a source/drain (S/D) structure 122’ over the fin structure 110, wherein the S/D structure 122’ is adjacent to the gate structure 114, and the S/D structure 122’ comprises a doped region (“B-doped “, par [0028]) at an outer portion 122C of the S/D structure 122’; a metal silicide layer 142 over the doped region (“B-doped “, par [0021]), wherein the gate spacer layer 116 intersects with the fin structure 110, the doped region (“B-doped “, par [0028]), and the metal silicide layer 142; and a metal layer 144 adjacent to the metal silicide layer 142, wherein a bottom surface of the metal layer 144 is substantially level (bottom of 144 level with bottom of 142) with a bottom surface of the metal silicide layer 142.
With regards to claim 13, figs. 6a and 12 of Tsai discloses that the S/D structure 122’ comprises an upwardly facing facet (top surface of 122’) and a downwardly facing facet (downward facing sidewalls of 122’), and a bottom surface of the gate spacer layer (bottom of 116) extends to a point (extends from above 122’ to below the point where the top and sidewall of 122’ intersect) that the upwardly facing facet (top surface of 122’) and the downwardly facing facet (downward facing sidewalls of 122’) intersect.
With regards to claim 14, figs. 6a and 12 of Tsai discloses that the doped region 122C is formed on the upwardly facing facet (top of 122’) and separated from the downwardly facing facet (downward facing sidewalls of 122’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2016/0111537) in view of Guo (US 2018/0197793).
With regards to claim 3, fig. 12 of Tsai discloses that the doped region has a first portion on upwardly facing facets (top surfaces of 122’) of the S/D structure 122’ and a second portion (downward facing side surfaces of 122’) on the downwardly facing facets of the S/D structure 122’.
Tsai does not disclose a doping concentration of the first portion of the doped region is greater than a doping concentration of the second portion of the doped region.
However, fig. 9 of Guo discloses a doping concentration of the first portion 200 of the doped region is greater (“p-type dopant ion implantation process dopes a top portion of the doped region 124 (forming the doped region 200)”, par [0059]) than a doping concentration of the second portion 124 of the doped region.
Therefore, it would have been obvious to one of ordinary skill in the art to form the source and drain regions of Tsai with the extra doped region as taught in Guo in order to reduce the source/drain contact resistance. See par [0034] of Guo.
With regards to claim 4, Tsai does not disclose a sidewall spacer on opposite sidewall surfaces of the S/D structure, wherein the sidewall spacer is separated from the doped region.
However, fig. 9 of Guo discloses a sidewall spacer 112 on opposite sidewall surfaces of the S/D structure 102, wherein the sidewall spacer 112 is separated from the doped region 200.
Therefore, it would have been obvious to one of ordinary skill in the art to form the fins of Tsai with the sidewalls as taught in Guo in order to provide a liner between the semiconductor fins and the dielectric layer. See par [0040] of Guo.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2016/0111537), Guo (US 2018/0197793), and Lee (US 2016/0307927).
With regards to claim 5, Tsai does not disclose the metal silicide layer is sandwiched between the sidewall spacer and the metal layer.
Tsai does not disclose the metal silicide layer is sandwiched between the sidewall spacer and the metal layer.
However, fig. 5 of Lee discloses the metal silicide layer 320 is sandwiched between the sidewall spacer 220 and the metal layer 330.
Therefore, it would be obvious to one of ordinary skill in the art to form the source/drain region of Tsai with the metal silicide and spacer as taught in Lee in order to provide a low resistance contact to the source drain region. See par [0049] of Lee.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2016/0111537) in view of Clevenger et al. (US 2018/0076086) (“Clevenger”).
With regards to claim 9, fig. 12 of Tsai discloses that an inter-layer dielectric (ILD) layer 126 surrounding the S/D structure 122’.
Xie does not disclose a bottom surface of the gate spacer layer is lower than a bottom surface of the ILD layer.
However, fig. 1(c) of Clevenger discloses a bottom surface (bottom of 104) of the gate spacer layer 104 is lower than a bottom surface of the ILD layer 110.
Therefore, it would have been obvious to one of ordinary skill in the art to form the inter-layer dielectric layer of Tsai with the outer liner as taught in Clevenger in order to provide an etch stop layer. See par [0030] of Clevenger.
With regards to claim 10, Tsai does not disclose a contact etch stop layer (CESL) sandwiched between the ILD layer and the fin structure.
However, fig. 1(c) of Clevenger discloses a contact etch stop layer (CESL) 1106 sandwiched between the ILD layer 110 and the fin structure 102.
Therefore, it would have been obvious to one of ordinary skill in the art to form the inter-layer dielectric layer of Tsai with the outer liner as taught in Clevenger in order to provide an etch stop layer. See par [0030] of Clevenger.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2016/0111537) and Lee (US 2016/0307927).
With regards to claim 12, Tsai does not disclose a metal nitride layer over the metal silicide layer, wherein a sidewall of the metal nitride layer is substantially flush with a sidewall of the metal silicide layer.
However, fig. 5 of Lee discloses a metal nitride layer (“metal nitride”, par [0080]) over the metal silicide layer 320, wherein a sidewall of the metal nitride layer (“metal nitride”, par [0080]) is substantially flush with a sidewall of the metal silicide layer 320.
Therefore, it would have been obvious to one of ordinary skill in the art to form the contact plug of Tsai with the metal nitride as taught in Lee in order to provide a diffusion barrier. See par [0080] of Lee.
Allowable Subject Matter
Claims 6-7 and 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, Tsai (US 2016/0111537), Guo (US 2018/0197793), and Lee (US 2016/0307927) do not disclose a top surface of the sidewall spacer is higher than a top surface of the metal layer.
Regarding claim 7, Tsai (US 2016/0111537), Guo (US 2018/0197793), and Lee (US 2016/0307927) do not disclose that the metal layer and the metal silicide layer comprise the same metal element.
Regarding claim 11, Tsai (US 2016/0111537), Xie (US 10,199,271), and Clevenger (US 2018/0076086) do not disclose the ILD layer is doped with gallium (Ga), and gallium (Ga) doping concentration of the ILD layer increases gradually from bottom to top.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowance of claim 15 is that the closest prior arts Tsai (US 2016/0111537), Xie (US 10,199,271), Guo (US 2018/0197793), and Lee (US 2016/0307927) do not disclose that the metal silicide layer overlaps with the sidewall spacer and the metal layer in a direction that is perpendicular to the sidewall surfaces of the S/D structure. Claims 16-20 depend on claim 15 and area also allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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