DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Both the gate dielectric layer in par [0044] and a merged S/D structure in par [0082] are labeled 134.
Appropriate correction is required.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because in fig. 3E the gate dielectric is labeled 136 but 136 is not described in the specification. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 10,199,271) (“Xie”).
With regard to claim 1, figs. 17-18 of Xie discloses a fin field effect transistor (FinFET) device structure, comprising: a plurality of fin structures 104 above a substrate 102; an isolation structure 110 over the substrate 102 and between the fin structures 104; a gate structure formed over the fin structure; a source/drain (S/D) structure over the fin structure104 , wherein the S/D structure 106 is adjacent to the gate structure 414; and a metal silicide layer over the S/D structure 106, wherein the metal silicide layer 382 is in contact with the isolation structure 110.
With regard to claim 2, fig. 17 of Xie discloses the S/D structure 106 comprises a doped region (“P-type dopants”, col. 6 ll. 21) at an outer portion of the S/D structure, and the doped region comprises gallium (Ga) (“gallium (Ga)”, col. 6 ll. 22) or boron (B).
With regard to claim 8, figs. 17-18 of Xie discloses a fin field effect transistor (FinFET) device structure, comprising: a fin structure 104 over a substrate 102; a gate structure 414 formed over the fin structure 104; a gate spacer layer (“spacer structures”, col. 6 ll. 9) on opposite sidewall surfaces of the gate structure 414; a source/drain (S/D) structure 106 over the fin structure 104, wherein the S/D structure 106 is adjacent to the gate structure 414, and the S/D structure 106 comprises a doped region (“doped region”, col. 6 ll. 18-19) at an outer portion of the S/D structure 106; and a metal silicide layer 382 over the doped region (“doped region”, col. 6 ll. 18-19), wherein the gate spacer layer (“spacer structures”, col. 6 ll. 9) intersects with the fin structure 104, the doped region (“doped region”, col. 6 ll. 18-19), and the metal silicide layer 382.
With regard to claim 12, figs. 17-18 of Xie disclose a metal nitride layer (“liner may include any conventional liner material such as titanium nitride (TiN)”, col. 7 ll. 23-25) over the metal silicide layer 382, wherein a sidewall of the metal nitride layer (“TiN”, col. 25) is substantially flush with a sidewall of the metal silicide layer 382.
With regard to claim 13, figs. 17-18 of Xie discloses that the S/D structure 106 comprises an upwardly facing facet (top of 106) and a downwardly facing facet (bottom of 106), and a bottom surface of the gate spacer layer (“spacer structures”, col. 6 ll. 6) extends to a point that the upwardly facing facet (top of 106) and the downwardly facing facet (bottom of 106) intersect.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 10,199,271) (“Xie”) in view of Guo et al. (US 2018/0197793) (“Guo”).
With regard to claim 3, fig. 17 of Xie discloses that the doped region has a first portion on upwardly facing facets (top surfaces of 106) of the S/D structure 106 and a second portion (bottom surfaces of 106) on the downwardly facing facets of the S/D structure 106.
Xie does not disclose a doping concentration of the first portion of the doped region is greater than a doping concentration of the second portion of the doped region.
However, fig. 9 of Guo discloses a doping concentration of the first portion 200 of the doped region is greater (“p-type dopant ion implantation process dopes a top portion of the doped region 124 (forming the doped region 200)”, par [0059]) than a doping concentration of the second portion 124 of the doped region.
Therefore, it would have been obvious to one of ordinary skill in the art to form the source drain regions of Xie with the extra doped region as taught in Guo in order to reduce the source/drain contact resistance. See par [0034] of Guo.
With regard to claim 4, Xie does not disclose a sidewall spacer on opposite sidewall surfaces of the S/D structure, wherein the sidewall spacer is separated from the doped region.
However, fig. 9 of Guo disclose a sidewall spacer 112 on opposite sidewall surfaces of the S/D structure 102, wherein the sidewall spacer 112 is separated from the doped region 200.
Therefore, it would have been obvious to one of ordinary skill in the art to form the fins of Xie with the sidewalls as taught in Guo in order to provide a liner between the semiconductor fins and the dielectric layer. See par [0040] of Guo.
With regard to claim 14, Xie does not disclose that the doped region is formed on the upwardly facing facet and separated from the downwardly facing facet.
However, fig. 9 of Guo discloses that the doped region 200 is formed on the upwardly facing facet (top part of 124) and separated from the downwardly facing facet (bottom of 124).
Therefore, it would have been obvious to one of ordinary skill in the art to form the source drain regions of Xie with the extra doped region as taught in Guo in order to reduce the source/drain contact resistance. See par [0034] of Guo.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 10,199,271) (“Xie”), Guo et al. (US 2018/0197793) (“Guo”), and Lee et al. (US 2016/0307927) (“Lee”).
With regard to claim 5, fig. 17 of Xie discloses a metal layer 380 over the isolation structure 110.
Xie does not disclose the metal silicide layer is sandwiched between the sidewall spacer and the metal layer.
However, fig. 5 of Lee discloses the metal silicide layer 320 is sandwiched between the sidewall spacer 220 and the metal layer 330.
Therefore, it would be obvious to one of ordinary skill in the art to form the source/drain region of Xie with the metal silicide and spacer as taught in Lee in order to provide a low resistance contact to the source drain region. See par [0049] of Lee.
With regard to claim 7, fig. 17 of Xie discloses that the metal layer 380 and the metal silicide layer 382 comprise the same metal element (“titanium (Ti)”, col. 7 ll. 27; “titanium”, col. 15 ll. 29).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 10,199,271) (“Xie”) in view of Clevenger et al. (US 2018/0076086) (“Clevenger”).
With regard to claim 9, figs. 17-18 of Xie disclose that an inter-layer dielectric (ILD) layer 206 surrounding the S/D structure 106.
Xie does not disclose a bottom surface of the gate spacer layer is lower than a bottom surface of the ILD layer.
However, fig. 1(c) of Clevenger discloses a bottom surface (bottom of 104) of the gate spacer layer 104 is lower than a bottom surface of the ILD layer 110.
Therefore, it would have been obvious to one of ordinary skill in the art to form the initial dielectric layer of Xie with the outer liner as taught in Clevenger in order to provide an etch stop layer. See par [0030] of Clevenger.
With regard to claim 10, Xie does not disclose a contact etch stop layer (CESL) sandwiched between the ILD layer and the fin structure.
However, fig. 1(c) of Clevenger discloses a contact etch stop layer (CESL) 1106 sandwiched between the ILD layer 110 and the fin structure 102.
Therefore, it would have been obvious to one of ordinary skill in the art to form the initial dielectric layer of Xie with the outer liner as taught in Clevenger in order to provide an etch stop layer. See par [0030] of Clevenger.
Allowable Subject Matter
Claims 6 and 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowance of claim 15 is that the closest prior arts Xie et al. (US 10,199,271) (“Xie”), Guo et al. (US 2018/0197793) (“Guo”), and Lee et al. (US 2016/0307927) (“Lee”) do not disclose that the metal silicide layer overlaps with the sidewall spacer and the metal layer in a direction that is perpendicular to the sidewall surfaces of the S/D structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893