Prosecution Insights
Last updated: October 01, 2026
Application No. 18/521,931

METAL SOURCE/DRAIN FEATURES

Non-Final OA §102§103§112
Filed
Nov 28, 2023
Priority
Mar 31, 2020 — divisional of 11/424,338 +1 more
Examiner
TURNER, BRIAN
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
641 granted / 769 resolved
+23.4% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
51 currently pending
Career history
820
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
61.8%
+21.8% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 769 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “thin” in claims 1, 9 and 17 is a relative term which renders the claim indefinite. The term “thin” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purposes of compact prosecution, the Examiner has interpreted claims 1, 9 and 17 to mean: “…plurality of Claims 2-8, 10-16 and 18-20 depend on claims 1, 9 and 17, and are rejected under 35 USC § 112(b) for the same reasons. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rachmady et al. (PG Pub. No. US 2020/0279916 A1). Regarding claim 1, Rachmady teaches a method (fig. 4), comprising: receiving a workpiece (fig. 1: 100) comprising: a plurality of nanostructures (¶ 0052: plurality of bodies 130) extending between two dummy source/drain features (¶¶ 0026, 0051: sacrificial material defining source/drain regions 132, contacting opposing body sidewalls 133), a metal gate structure (¶¶ 0023, 0038, 0076: gate 161, including portions 163 and 165, of a gate-first process, including at least one metal) wrapping around each of the plurality of nanostructures (fig. 2A among others: 163/165 wraps around 130), and a dielectric layer (¶ 0033: 181) over the two dummy source/drain features (fig. 2A: 181 disposed over sacrificial 132); forming a top opening in the dielectric layer to expose the two dummy source/drain features (¶ 0033 & fig. 2A: at least one top opening formed in 181 to expose top surface of sacrificial 132); selectively removing the two dummy source/drain features to expose sidewalls of the plurality of nanostructures (¶¶ 0051, 0058: method step 412 includes recessing sacrificial 132 to form pockets by etching through upper fin portion 114 into lower fin portion 112); forming a plurality of thin epitaxial layers (¶ 0063: step 416 includes forming replacement source and drain regions 132) over the exposed sidewalls of the plurality of nanostructures (fig. 2A & ¶ 0063: replacement 132 directly connected to and extend laterally from sidewalls 133 of body 130); and forming a metal feature (¶ 0078: 140) over the plurality of thin epitaxial layers (fig. 2A: 140 formed over replacement 132). Regarding claim 2, Rachmady teaches the method of claim 1, wherein the plurality of nanostructures comprise silicon (Si) (¶¶ 0028, 0063: in at least one embodiment, 130 comprises silicon). Regarding claim 5, Rachmady teaches the method of claim 1, wherein, before the selectively removing, the two dummy source/drain features are in contact with sidewalls of the plurality of nanostructures (¶ 0063: replacement source/drain regions 132 directly connected to and extend laterally from the body 130). Regarding claim 6, Rachmady teaches the method of claim 1, wherein the two dummy source/drain features comprise silicon germanium (SiGe) (¶ 0062: in at least one embodiment, 132 comprises SiGe). Claims 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. (PG Pub. No. US 2020/0287020 A1). Regarding claim 17, Seo teaches a method (figs. 1-24), comprising: providing a workpiece (fig. 2) comprising: a substrate (¶ 0038: 110), a fin-shaped structure (¶ 0038: 115) disposed over the substrate (fig. 2: 115 disposed over 110) and comprises a plurality of channel layers interleaved by a plurality of sacrificial layers (¶ 0038 & fig. 2: 115 comprises a plurality of nanosheet layers 130 interleaved with a plurality of sacrificial layers 120), and a dummy gate stack (¶ 0042: 165) disposed over a channel region of the fin-shaped structure (fig. 2: 150 disposed over central region of 115, subsequently formed into nanosheet segments, meeting the broadest reasonable interpretation of a “channel region”); depositing a gate spacer layer over the dummy gate stack (¶ 0050: spacer layer, not illustrated, deposited over 165); etching a source/drain region of the fin-shaped structure to form a source/drain trench to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers (¶ 0053 & fig. 3: etching process forms stacks 116 with exposed sidewall surfaces of 120 and 130, creating trenches for subsequent source/drain formation); forming a dummy source/drain feature (¶ 0066: 190 and/or 200) in the source/drain trench (fig. 8: 190/200 formed in source/drain trench regions); replacing the dummy gate stack with a metal gate structure (¶ 0109 & fig. 21: 165 replaced with gate structure including metal fill 320); after the replacing, removing the dummy source/drain feature from the source/drain trench (¶ 0114 & fig. 23: 190/200 removed to expose sidewalls of nanosheet segments 132); forming a plurality of thin epitaxial conductive layers (¶ 0115: 330) over end surfaces of the plurality of channel layers (fig. 23: 330 formed over end surface of nanosheet segments 132); and forming a metal feature (¶ 0118: 34) in the source/drain trench (fig. 24: 340 formed in source/drain region over 330). Regarding claim 18, Seo teaches the method of claim 17, further comprising: before the forming of the dummy source/drain feature, selectively recessing end surfaces of the plurality of sacrificial layers in the channel region to form inner spacer recesses (¶ 0057: portions of the sacrificial sheet segments 122 exposed on opposite sides of the dummy gate structures 165 selectively removed to form cavities above and below semiconductor nanosheet segments 132); and forming inner spacer features (¶ 0058: 180) in the inner spacer recesses (fig. 5: 180 formed in cavities adjacent to 122). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 3-4, 9-10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady in view of Lee et al. (PG Pub. No. US 2019/0074362 A1). Regarding claim 3, Rachmady teaches the method of claim 1, including selectively removing the two dummy source/drain features (¶ 0063: sacrificial 132 selectively removed). Rachmady does not explicitly teach wherein, before the selectively removing, the metal gate structure is spaced apart from the two dummy source/drain features by a plurality of inner spacer features. Lee teaches a method including selectively removing at least portions of two source/drain features (¶¶ 0148, 0151 & figs. 19, 21: at least portions of 150 selectively removed), wherein, before the selectively removing, a metal gate structure (¶ 0032: 120, similar to 161 of Rachmady) is spaced apart from the two source/drain features by a plurality of inner spacer features (¶ 0050 & fig. 18: 120 spaced apart from 150 by inner spacers 141). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Rachmady to include inner spacer features, as a means to improve electrical isolation between the metal gate structure and the replacement source and drain features. Regarding claim 4, Rachmady in view of Lee teaches the method of claim 3, wherein the plurality of nanostructures are vertically interleaved by the plurality of inner spacer features (Lee, fig. 18: plurality of 110/210/310 interleaved with inner spacers 141). Regarding claim 9, Rachmady teaches a method (fig. 4), comprising: receiving a workpiece (fig. 2A: 100) comprising: a fin structure (¶ 0023: 110, including portions 112 and 114) comprising a channel region (¶ 0029, fig. 2A: middle region of 112 and/or 114) and a source/drain region (¶ 0051, fig. 2A: end regions of 112 and/or 114), a plurality of nanostructures (¶ 0052: plurality of bodies 130) disposed over the channel region of the fin structure (fig. 2A: 130 dispose in middle region of 114), a dummy source/drain feature (¶ 0051: sacrificial material source/drain regions 132) disposed over the source/drain region of the fin structure and in contact with sidewalls of the plurality of nanostructures (¶¶ 0051, 0063: sacrificial source and drain regions 132 directly connected to and extend laterally from the body 130 of upper fin portion 114), a metal gate structure (¶¶ 0023, 0038, 0076: gate 161, including portions 163 and 165, of a gate-first process, including at least one metal) wrapping around each of the plurality of nanostructures (fig. 2A: 163/165 wrap around 130), and a dielectric layer (¶ 0055: 181) over the dummy source/drain feature (fig. 2A: 181 disposed over sacrificial 132); forming a top opening in the dielectric layer to expose a top surface of the dummy source/drain feature (¶ 0033 & fig. 2A: at least one top opening formed in 181 to expose top surface of sacrificial 132); selectively removing the dummy source/drain feature to expose sidewalls of the plurality of nanostructures (¶¶ 0051, 0058: method step 412 includes recessing sacrificial 132 to form pockets by etching through upper fin portion 114 into lower fin portion 112, exposing sidewalls 133 of body 130); forming a plurality of thin epitaxial layers (¶ 0063: step 416 includes forming replacement source and drain regions 132) over the exposed sidewalls of the plurality of nanostructures (fig. 2A & ¶ 0063: replacement 132 directly connected to and extend laterally from sidewalls 133 of body 130); and forming a metal feature (¶ 0078: 140) over the plurality of thin epitaxial layers (fig. 2A: 140 formed over replacement 132). Rachmady does not teach the fin structure (110) is disposed between a first isolation feature and a second isolation feature along a direction. Lee teaches a method including receiving a workpiece (fig. 15) comprising a fin structure (¶ 0034: fin structure F, similar to 110 of Rachmady) disposed between a first isolation feature and a second isolation feature along a direction (¶ 0037 & fig. 15: F disposed between isolation features 105 along the Y1 direction) and comprising a channel region and a source/drain region (figs. 15-16: F includes channel regions and source/drain regions along the X1 direction), a plurality of nanostructures (¶ 0132: 112, similar to 130 of Rachmady) disposed over the channel region of the fin structure (fig. 16: 112 disposed over channel region of F). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the fin structure of Rachmady between first and second isolation features, as a means to minimize leakage between a substrate region and the bottom fin region, improving electrical properties of the device. Regarding claim 10, Rachmady in view of Lee teaches the method of claim 9, wherein the metal feature comprises cobalt (Co), ruthenium (Ru), or tungsten (W) (Rachmady, ¶ 0078: 140 includes tungsten). Regarding claim 16, Rachmady in view of Lee teaches the method of claim 9, wherein the plurality of nanostructures comprise silicon (Si) (Rachmady, ¶ 0063: 130 comprises Si), wherein the dummy source/drain feature comprise silicon germanium (SiGe) (Rachmady, ¶¶ 0051, 0063: sacrificial 132 comprises SiGe). Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady as applied to claim 6 above, and further in view of Peng et al. (PG Pub. No. US 2018/0090570 A1). Regarding claims 7-8, Rachmady teaches the method of claim 6, wherein the selectively removing comprises use of selective etch process (¶ 0059: removing sacrificial source/drain regions 132 includes a selective etch process). Rachmady does not explicitly teach the selective etch process is a wet etch, wherein the selectively removing comprises use of a mixture of ammonia hydroxide, hydrogen peroxide, and water. Peng teaches a method of selectively removing silicon germanium regions with a wet etch process (¶¶ 0058, 0072: silicon germanium regions 102a selectively removed with APM, which implicitly includes ammonia hydroxide, hydrogen peroxide, and water). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the selective etch process of Rachmady with the wet etch mixture of Peng, as a means to optimize the selectivity of the dummy source/drain feature removal (Peng, ¶ 0058). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Seo as applied to claim 17 above, and further in view of Coquand et al. (PG Pub. No. US 2019/0198616 A1). Regarding claim 19, Seo teaches the method of claim 17, comprising forming of a metal feature (340) and a plurality of epitaxial layers (330). Seo fails to teach the method further comprising, before the forming of the metal feature, forming a plurality of silicide features over surfaces of the plurality of epitaxial layers. Coquand teaches a method including forming a plurality of silicide features (¶ 0087: 131) over surfaces of a plurality of epitaxial layers (¶ 0084 & fig. 9: 131 formed over layers 118, including portions of epitaxial layers 104), and forming of a metal feature (¶¶ 0070, 0091: 120). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Seo with a plurality of silicide features formed over surfaces of the plurality of epitaxial layers, as a means to reduce contact electrical resistance value between channel extension regions and source and drain regions of the FET transistor (Coquand, ¶ 0004). Allowable Subject Matter Claims 11-14 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating: “the workpiece further comprises: a first dielectric feature disposed on the first isolation feature; and a second dielectric feature disposed on the second isolation feature, wherein the dummy source/drain feature is sandwiched between the first dielectric feature and the second dielectric feature along the direction” as recited in claim 11, and “wherein the dummy source/drain feature comprises silicon germanium (SiGe), wherein the removing of the dummy source/drain feature comprises use of a mixture of ammonia hydroxide, hydrogen peroxide, and water” as recited in claim 20. Claims 12-14 depend on claim 11 and would be allowable for the same reasons indicated above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/ Examiner, Art Unit 2818
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Prosecution Timeline

Nov 28, 2023
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+4.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 769 resolved cases by this examiner. Grant probability derived from career allowance rate.

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