DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7 in the reply filed on 03/23/2026 is acknowledged.
Claims 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claims 1-7 have been fully considered in Examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2019/0088567A1) in view of Lin (U.S. PG Pub No US2015/0061102A1) and An (U.S. PG Pub No US2022/0093829A1).
Regarding claim 1, Chang teaches a LED (light emitting diode) package structure [see fig. 3, 0045], comprising:
a substrate (10) fig. 3 [0045] having a first (top) surface and a second (bottom) surface opposite to each other;
a conductive structure (14) fig. 3 [0044] including a first conductive structure (CS1 of 14) see annotated fig. 3 below [0044] and a second conductive structure (CS2 of 14) see annotated fig. 3 below [0044] that are electrically connected with each other (through electrically-conductive copper material of 14) [0043-0045], wherein the first conductive structure (CS1) is disposed on (supported by) the first (top of 10) surface, and the second conductive structure (CS2) is disposed on (supported by) the second (bottom of 10) surface;
a first gold layer (upper 22) fig. 3 [0045] (formed of Au/gold) [0045] disposed on (supported by) the first conductive structure (CS1);
a second gold layer (lower 22) fig. 3 [0045] (formed of Au/gold) [0045] disposed on (supported by) the second conductive structure (CS2);
an LED chip (80) fig. 3 [0041, 0045] disposed on (supported by) the first gold layer (upper 22).
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (CS2)][AltContent: textbox (CS1)][AltContent: rect][AltContent: rect]
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216
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Annotated fig. 3 of Chang
However, Chang does not explicitly disclose a thickness of the first gold layer (upper 22) fig. 3 [0044] being greater than 1 μm (0.05-20 μm) [0045],
the second conductive structure (CS2) being completely covered by the second gold layer (upper 22) (sidewalls are not covered),
a package layer disposed on the first (top of 10) surface, wherein the first conductive structure (CS1), the first gold layer (upper 22), and the LED chip (80) are encapsulated by the package layer.
Chang discloses a thickness of the first gold layer (upper 22) fig. 3 [0045] being greater than 1 μm (0.05-20 μm) [0045] (could be implemented with a thickness 1 to 20 μm [0045]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness of the first gold layer of Chang to be in the upper end of the recited range [0045] such that the thickness is greater than 1 micron [0045] in order to ensure sufficient amount of electrically conductive gold material for electrical connections [0045] and to ensure a strong bond with the overlying pad [0045], as taught by Chang.
However, Chang does not explicitly the second conductive structure (CS2) being completely covered by the second gold layer (upper 22) (sidewalls are not covered),
a package layer disposed on the first (top of 10) surface, wherein the first conductive structure (CS1), the first gold layer (upper 22), and the LED chip (80) are encapsulated by the package layer.
Lin teaches an LED package structure [see fig. 14, 0056] comprising the second conductive structure (170) fig. 14 [0056] being completely covered (sidewalls and bottom of 170 covered; rest covered by 140) by the second gold layer (216) fig. 14 [0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LED package structure of Chang such that the gold layer also covers the sidewalls of the conductive structure [0056] in order to extend the oxidation protection offered by the gold layer [0051] over the sidewalls of the covered, conductive layer(s) [0051, 0056], as taught by Lin.
However, Chang in view of Lin does not explicitly disclose a package layer disposed on the first (top of 10) surface, wherein the first conductive structure (CS1), the first gold layer (upper 22), and the LED chip (80) are encapsulated by the package layer.
An teaches an LED package structure [see fig. 4a, 0035] comprising a package layer (31) fig. 4a [0035] disposed on the first surface (top of 15) fig. 4a [0035], wherein the first conductive structure (18a; portion of 18 above 15) fig. 4a [0035], the first gold layer (represented by 12; formed of gold in Chang’s package) fig. 4a [0035-0037], and the LED chip (11a) fig. 4a [0035] are encapsulated by the package layer (31).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Chang in view of Lin to have included the encapsulating layer [0035] of An in order to provide the package with additives in the molding compound [0032] that improve package heat dissipation [0032] and/or package optical reflectance [0032, 0035], as taught by An.
Regarding claim 2, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 1. However, Chang does not explicitly disclose wherein a thickness of the second gold layer (lower 22) fig. 3 [0044] is less than 1 μm.
Chang discloses a thickness of the second gold layer (lower 22) fig. 3 [0045] is less than 1 μm (0.05-20 μm) [0045] (could be implemented with a thickness 0.05 to 1 μm [0045]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness of the first gold layer of Chang to be in the lower end of the recited range [0045] such that the thickness is less than 1 micron [0045] in order to ensure sufficient amount of electrically conductive gold material for electrical connections [0045] without using an unnecessary, excessive amount of costly gold material [0013], as taught by Chang.
Regarding claim 3, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 1. Chang also teaches wherein a nickel layer (upper 20) fig. 3 [0044] is disposed between the first gold layer (upper 22) fig. 3 [0044] and the first conductive structure (CS1 of 14) see annotated fig. 3 above [0044].
Regarding claim 4, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 1. Chang also teaches wherein a nickel layer (lower 20) fig. 3 [0044] is disposed between the second gold layer (lower 22) fig. 3 [0044] and the second conductive structure (CS2 of 14) see annotated fig. 3 above [0044].
Regarding claim 5, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 4. However, Chang does not explicitly disclose wherein a palladium layer is disposed between the second gold layer (lower 22) fig. 3 [0044] and the nickel layer (lower 20) fig. 3 [0044].
Lin teaches an LED package structure [see fig. 14, 0056] wherein a palladium layer (214) fig. 14 [0056] is disposed between the second gold layer (216) fig. 14 [0044] and the nickel layer (212) fig. 14 [0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LED package structure of Chang such that a palladium layer is provided between the nickel and gold layers [0056] in order to increase the amount of conductive material in the under bump metallization layers [0051] comprising nickel and gold [0051, 0056] so as to improve the reliability of electrical connections formed with the under bump metallization layers [0051, 0056], as taught by Lin.
Regarding claim 6, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 1. Chang also teaches wherein a conductive layer (12) fig. 3 [0043] (electrically-conductive titanium metal) [0043] is disposed between the substrate (10) fig. 3 [0044] and the conductive structure (14) fig. 3 [0044].
Regarding claim 7, Chang in view of Lin and An teaches the LED package structure [see fig. 3, 0045] of claim 1. Chang also teaches wherein the LED chip (80) fig. 3 [0041, 0045] is connected [0044-0045] with the first gold layer (upper 22) fig. 3 [0045] (formed of Au/gold) [0045] via a gold connector (81) fig. 3 [0045] (formed of gold-based electrically conductive Au-Sn alloy) [0045].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature LED package structures with interconnects in through holes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/08/2026
