Prosecution Insights
Last updated: October 22, 2026
Application No. 18/522,634

METHOD OF MAKING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Nov 29, 2023
Priority
Jul 29, 2011 — divisional of 9905524 +2 more
Examiner
PAYEN, MARVIN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
367 granted / 474 resolved
+9.4% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
5 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.0%
+21.0% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 474 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Election/Restrictions Applicant's election with traverse of Group I (claims 1-8 and 16-20) in the reply filed on 18 May 2026 is acknowledged. The traversal is on the grounds that “Applicant respectfully traverses the asserted Restriction Requirement as not imposing a serious burden on the Examiner. The Office asserted that the feature of a protective layer directly contacting the conductive pad provides a different scope between the asserted Groups. By this Amendment, claim 9 is amended to include this feature. Thus, no serious burden exists on the Examiner to examine all claims 1-20.” This is not found persuasive because the issue and burden is not simply “a protective layer”, but also the claim limitations including but not limited to a first and second mask layers, as in the context of claim 9. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kuechenmeister et al. (2010/0164098, from hereinafter “Kuechenmeister”) in view Kang et al. (2011/0283034, from hereinafter “Kang”), and further in view of Hwang et al. (2012/0007230, from hereinafter “Hwang”). Re Claim 1. Kuechenmeister discloses in Figs. 2a-2i, a method of making a semiconductor device comprising: patterning a conductive layer (211) over a substrate (201) to define a conductive pad having a first width; depositing a passivation layer (212A) over the conductive pad, wherein the passivation layer directly contacts the conductive pad; depositing a protective layer (212B) over the passivation layer; and forming a conductive pillar (261) in the opening. Kuechenmeister fails to disclose: depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width; depositing a mask layer over the UBM layer; forming an opening in the mask layer wherein the opening has the second width; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width. However, Kang discloses: depositing an under-bump metallization (UBM) layer (Fig. 12C; 145) directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width; depositing a mask layer (Fig. 12E; 147) over the UBM layer; forming an opening (Fig. 12D) in the mask layer wherein the opening has the second width; and etching the UBM layer (Fig. 12F) using the conductive pillar as a mask, wherein the etched UBM layer has the second width. Therefore, the claim would have been obvious to one of ordinary skill in the art at the time the invention was made because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, and “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp.” KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007). In addition, Kuechenmeister/Kang fails to disclose: wherein the protective layer directly contacts the conductive pad. However, Hwang discloses in Fig. 3: wherein a protective layer (113) directly contacts a conductive pad (107). Re Claim 2. Kang discloses, further comprising defining a passivation opening in the passivation layer to expose a first portion of the conductive pad, wherein a width of the passivation opening is a third width less than the first width. Re Claim 3. Hwang discloses in Fig. 3, wherein depositing the protective layer comprises depositing the protective layer into the passivation opening. Re Claim 4. Hwang discloses in Fig. 3, further comprising defining a protective opening in the protective layer to expose a second portion of the conductive pad, wherein a width of the protective opening is a fourth width less than the first width. Re Claim 5. Hwang discloses in Figs. 2-3, wherein the fourth width is less than the third width. Re Claim 6. Hwang discloses in Fig. 4, wherein depositing the UBM layer comprises depositing the UBM layer into the protective opening. Re Claim 7. Hwang discloses in Fig. 11, further comprising bonding the conductive pillar (123) to a conductive region (135, 137) of a substrate. Re Claim 8. Hwang discloses in Fig. 11, wherein bonding the conductive pillar (123) to the conductive region (135, 137) comprises bonding the conductive pillar using a solder joint (133). Claims 16-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kang, and further in view of Hwang. Re Claim 16. Kang discloses in Figs. 6-7, a semiconductor device comprising: a plurality of conductive pads (104), wherein each conductive pad of the plurality of conductive pads has a first width; a passivation layer (132) over each of the plurality of conductive pads, wherein the passivation layer directly contacts each of the plurality of conductive pads; a protective layer (134) over the passivation layer; a plurality of under-bump metallization (UBM) layers (145), wherein each UBM layer of the plurality of UBM layers directly contacting a corresponding conductive pad of the plurality of conductive pads, and each of the plurality of UBM layers has a second width greater than the first width; and a plurality of conductive pillars (146, 146b), wherein each conductive pillar of the plurality of conductive pillars is on a corresponding UBM layer of the plurality of UBM layers, and adjacent conductive pillars of the plurality of conductive pillars are separated by a pitch. Kang fails to disclose: wherein the protective layer directly contacts each of the plurality of conductive pads. However, Hwang discloses in Fig. 3: wherein a protective layer (113) directly contacts a plurality of conductive pads (107). Therefore, the claim would have been obvious to one of ordinary skill in the art at the time the invention was made because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, and “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp.” KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007). Re Claim 17. Kang discloses, wherein the passivation layer is continuous between adjacent conductive pillars of the plurality of conductive pillars. Re Claim 18. Kang discloses, wherein the protection layer is continuous between adjacent conductive pillars of the plurality of conductive pillars. Re Claim 19. Kang discloses, wherein the UBM layer is discontinuous between adjacent conductive pillars of the plurality of conductive pillars. Re Claim 20. Kang fails to disclose, further comprising a plurality of cap layers, wherein a cap layer of the plurality of cap layer is over a corresponding conductive pillar of the plurality of conductive pillars. However, Hwang discloses in Fig. 10, further comprising a cap layer (127), wherein a cap layer is over a corresponding conductive pillar (123). Therefore, the claim would have been obvious to one of ordinary skill in the art at the time the invention was made because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, and “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp.” KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARVIN PAYEN whose telephone number is (571)270-7435. The examiner can normally be reached on Monday-Thursday, Fridays off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARVIN PAYEN/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Nov 29, 2023
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
80%
With Interview (+2.8%)
2y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 474 resolved cases by this examiner. Grant probability derived from career allowance rate.

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