DETAILED ACTION
This action is responsive to the application No. 18/522,867 filed on November 29, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 04/09/2026 responding to the Office action mailed on 01/09/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Claim 3 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 8, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0299914) in view of Chang (US 2019/0067128).
Regarding Claim 1, Kim (see, e.g., Figs. 1-6), teaches a method for forming a semiconductor device structure comprising:
providing a substrate 100 comprising a plurality of trenches 111/112, wherein the plurality of trenches 111/112 comprise at least one NMOS gate trench 111 and at least one PMOS gate trench 112, wherein at least one of the plurality of trenches 111/112 comprises a sidewall and a bottom portion, wherein an interfacial layer 125 is disposed on a bottom portion and wherein a spacer 120 is disposed on the sidewall (see, e.g., Figs. 3-4, pars. 0033, 0035, 0036, 0046);
depositing a gate dielectric 130 over the plurality of trenches 111/112, wherein the gate dielectric 130 is conformally deposited on the spacer 120 extending from an opening of the trench 111/112 to the interfacial layer 125 (see, e.g., Fig. 4, par. 0058);
depositing a NMOS gate electrode 140/150 over the plurality of trenches 111/112 such that the NMOS gate electrode 140/150 spans a surface of the gate dielectric 130 in the plurality of trenches 111/11 (see, e.g., Fig. 4, par. 0036);
after depositing the NMOS gate electrode 140/150 removing at least a portion of the NMOS gate electrode 140/150 in the at least one PMOS gate trench 112 (see, e.g., Fig. 5, par. 0061); and
after removing at least a portion of the NMOS gate electrode 140/150 in the at least one PMOS gate trench 112, depositing a first work function metal 161/162 in the plurality of trenches 111/112 (see, e.g., Fig. 1, pars. 0036, 0047),
wherein depositing the NMOS gate electrode 140/150 comprises:
depositing a first liner layer 140 (see, e.g., par. 0039);
depositing a second work function metal 150 on the first liner layer 140 (see, e.g., par. 0042); and
depositing a second liner layer 150 comprising one or more of titanium nitride, tantalum nitride, or niobium nitride on the second work function metal 150 (see, e.g., par. 0042),
wherein the first work function metal 161 is deposited directly over the second liner layer 150 in the NMOS gate trench 111.
Kim is silent with respect to the claim limitations that the first liner layer 140 comprises titanium nitride and the second work function layer 150 comprises at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), and niobium aluminum carbide (NbAlC).
Kim discloses the claimed invention except for the use of LaO instead of titanium nitride for the first liner layer (see, e.g., par. 0039), and the use of TiN for the second work function metal instead of TiAlC. Chang, on the other hand teaches that LaO and TiN are equivalent materials known in the art and TiN and TiAlC are equivalent material known in the art (see, e.g., Chang, Fig. 15, par. 0047). Therefore, because these protection layers were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute TiN for LaO and TiAlC for TiN since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 2, Kim and Chang teach all aspects of claim 1. Kim (see, e.g., Figs. 1-6), teaches that the first work function metal 161/162 comprises Al, W, Ti or a combination thereof (see, e.g., par. 0044). Kim does not teach that the first work function metal comprises molybdenum.
Kim discloses the claimed invention except for the use of Al, W, Ti, instead of molybdenum for the first work function metal (see, e.g., par. 0044). Chang, on the other hand teaches that tungsten, aluminum, and molybdenum are equivalent materials known in the art (see, e.g., Chang, Fig. 19, par. 0058). Therefore, because these work function materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute tungsten or aluminum for molybdenum since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 4, Kim and Chang teach all aspects of claim 1. Kim (see, e.g., Figs. 1-6), teaches that the step of removing at least a portion of the NMOS gate electrode 140/150 comprises removing the second liner layer 150 (i.e., TaN) the second work function metal 150 (i.e., TiN), and at least a portion of the first liner layer 140 in the at least one PMOS gate trench 112 (see, e.g., Fig. 5, par. 0061).
Regarding Claim 5, Kim and Chang teach all aspects of claim 4. Kim (see, e.g., Figs. 1-6), teaches depositing a third liner layer TaN after removing at least a portion of the first liner layer 140 in the at least one PMOS gate trench 112 and before depositing a first work function metal 161 (i.e., Al) (see, e.g., Fig. 1, par. 0049).
Regarding Claim 8, Kim and Chang teach all aspects of claim 1. Kim (see, e.g., Figs. 1-6), teaches that removing at least a portion of the NMOS gate electrode 140/150 in the at least one PMOS gate trench 112 comprises forming a masking layer 135 in the at least one NMOS gate trench 111 and exposing the substrate 100 to an etchant (see, e.g., Fig. 5, par. 0061).
Regarding Claim 11, Kim teaches all aspects of claim 1. Kim (see, e.g., Figs. 1-6 and Chang (see, e.g., Fig. 15), teach that the second work function metal 150 comprises at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), or niobium aluminum carbide (NbAlC) (see, e.g., Chang, par. 0047).
Regarding Claim 12, Kim and Chang teach all aspects of claim 1. Kim (see, e.g., Figs. 1-6), teaches that the first liner layer 140 is deposited directly on the gate dielectric 130.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0299914) in view of Chang (US 2019/0067128), and further in view of Wang (US 2018/0175201).
Regarding Claim 6, Kim and Chang teach all aspects of claim 1. Kim is silent with respect to the claim limitation that depositing the gate dielectric 130 comprises a chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) process. Wang (see, e.g., Fig. 9), in similar processes to Kim, on the other hand, teaches that to achieve a conformal layer, the gate dielectric 56 is deposited by a PECVD process and the like (see, e.g., par. 0022).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the gate dielectric in Kim’s process by a chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) process, as taught by Wang, to achieve a conformal layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0299914) in view of Chang (US 2019/0067128) and further in view of Bao (US 2018/0315756).
Regarding Claim 7, Kim and Chang teach all aspects of claim 1. Kim does not teach that depositing the first work function metal 161/162 comprises a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.
Bao, in similar processes to Kim, on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033).
It would have been obvious to one of ordinary skill in the art at the time of filing to include an atomic layer deposition process in the method of Kim, as taught by Bao, to deposit a conformal metal gate.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0299914) in view of Chang (US 2019/0067128) and further in view of Park (US 9,275,834).
Regarding Claim 9, Kim and Chang teach all aspects of claim 8. Kim is silent with respect to the claim limitation that the etchant comprises at least one of sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or nitrogen trifluoride (NF3).
Park, on the other hand, teaches selectively etching TiN layers relative to metals/conductors, using NF3, SF6 to assist in removing oxidation (if present) on the titanium nitride and to avoid the formation of pits on the surfaces of some materials (see, e.g., col. 3, ll. 21-24, 54-63, col. 5, ll. 35-55).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kim’s process an etchant comprising at least one of sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or nitrogen trifluoride (NF3), as taught by Park, to assist in removing oxidation (if present) on the titanium nitride and to avoid the formation of pits on the surfaces of some materials.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0299914) in view of Chang (US 2019/0067128), Bao (US 2018/0315756) and further in view of Xiao (US 2017/0226636).
Regarding Claim 10, Kim and Chang teach all aspects of claim 1. Kim (see, e.g., Figs. 1-6), teaches depositing a first work function metal 161/162 (see, e.g., pars. 0036, 0047).
Kim is silent with respect to the claim limitations that depositing the first work function metal comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
Bao on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033), and Xiao, teaches contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor that is capable of reacting with the metal containing precursor to produce metal crystal growth on a heated surface (see, e.g., Xiao, pars. 0004, 0035).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the first work function metal comprising an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor, as taught by Bao and Xiao, to deposit a conformal molybdenum metal gate on a heated surface.
Regarding Claim 13, Kim, Chang, Bao, and Xiao teach all aspects of claim 10. Xiao teaches that the reducing agent precursor comprises hydrogen (H2) (see, e.g., par. 0035).
Claims 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Choi (US 2018/0090583).
Regarding Claim 14, Park (see, e.g., Figs. 1-9), teaches a method for forming a NMOS semiconductor device structure comprising:
providing a substrate 10 comprising at least one trench 30/31, wherein at least one of the plurality of trenches 30/31 comprises a sidewall and a bottom portion, wherein and interfacial layer 32/33 is disposed on the bottom portion, wherein a spacer 22/23 is disposed on the sidewall (see, e.g., Figs. 2, 3, pars. 0062, 0068);
depositing a gate dielectric layer 34a/35a over the at least one trench 30/31, wherein the gate dielectric layer 34a/35a is conformally directly deposited on the spacer 22/23 extending from an opening of the trench 30/31 to the interfacial layer 32/33 (see, e.g., Fig. 3, par. 0071);
depositing a NMOS gate electrode 37a/43a/45a such that the NMOS gate electrode 39a/43a/45a spans a surface of the gate dielectric 34a/35a in the plurality of trenches 30/31 (see, e.g., Fig. 7, pars. 0081, 0086, 0089); and
depositing a first work function metal 50a/51a in the at least one trench 30/31 (see, e.g., Fig. 7, par. 0090),
wherein depositing the NMOS gate electrode 37a/43a/45a comprises:
depositing a first liner layer 37a comprising titanium nitride (see, e.g., par. 0074);
depositing a second work function metal 43a comprising at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), and niobium aluminum carbide (NbAlC) (see, e.g., par. 0086), and
depositing a second liner layer 45a comprising one or more of titanium nitride, tantalum nitride, or niobium nitride (see, e.g., par. 0089),
wherein the first work function metal 51a is deposited directly over the second liner layer 45a, and wherein the first liner layer 37a is deposited directly on the gate dielectric layer 35a.
Park is silent with respect to the claim limitation that the first work function metal 50a/51a comprises molybdenum.
Park discloses the claimed invention except for the use of Al and/or W instead of molybdenum (Mo) for the first work function metal (see, e.g., par. 0091). Choi, on the other hand teaches that Al, W, and Mo are equivalent materials known in the art (see, e.g., Choi, Fig. 8A, par. 0031). Therefore, because these work function materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute Al and/or W for Mo since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 16, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches that the second liner layer 45a comprises tantalum nitride or niobium nitride (see, e.g., par. 0089).
Regarding Claim 17, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches that the second work function metal 43a comprises at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), or niobium aluminum carbide (NbAlC) (see, e.g., par. 0086).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Choi (US 2018/0090583) and further in view of Bao (US 2018/0315756) and Xiao (US 2017/0226636).
Regarding Claim 15, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches depositing a first work function metal 50a/51a (see, e.g., par. 0090).
Park is silent with respect to the claim limitations that depositing the first work function metal comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
Bao on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033), and Xiao, teaches contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor that is capable of reacting with the metal containing precursor to produce metal crystal growth on a heated surface (see, e.g., Xiao, pars. 0004, 0035).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the first work function metal comprising an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor, as taught by Bao and Xiao, to deposit a conformal molybdenum metal gate on a heated surface.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0090583) in view of Jang (US 2018/0174845).
Regarding Claim 18, Choi (see, e.g., Figs. 4A-8A), teaches a method for forming a PMOS semiconductor device structure 100 comprising:
providing a substrate 110 comprising at least one trench GH, wherein at least one of the plurality of trenches GH comprises a sidewall and a bottom portion, wherein an interfacial layer 112 is disposed on the bottom portion, wherein a spacer 124 is disposed on the sidewall (see, e.g., Figs. 6A, 7A, pars. 0022, 0026, 0027, 0054);
depositing a gate dielectric 114 over the at least one trench GH, wherein the gate dielectric 114 is conformally deposited on the spacer 124 extending from an opening of the trench GH to the interfacial layer 112 (see, e.g., Fig. 7A, par. 0026);
depositing a first liner layer 115a directly onto the gate dielectric 114 such that the first liner layer 115a spans a surface of the gate dielectric 114 in the plurality of trenches GH (see, e.g., Fig. 7A, par. 0030), wherein the first liner layer 115a comprises a titanium nitride film (TiN) (see, e.g., par. 0031); and
depositing a first work function metal 115b directly onto the first liner layer 115a, wherein the first work function metal 115b comprises molybdenum (see, e.g., Fig. 7A, pars. 0030-0031).
Choi is silent with respect to the claim limitation that the TiN film is doped with one or more of carbon (C), silicon (Si), or boron (B).
Jang (see, e.g., Figs. 1A-1C), on the other hand, teaches a doped metal nitride film 107 that is doped with a work function adjusting element comprising at least one of carbon, silicon, or boron for engineering the work function into a high work function or a low work function (see, e.g., pars. 0027-0028, 0078).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Choi’s process, the TiN film doped with one or more of carbon (C), silicon (Si), or boron (B), as taught by Jang, for engineering the work function into a high work function or a low work function.
Regarding Claim 20, Choi and Jang teach all aspects of claim 18. Jang (see, e.g., Figs. 1A-1C), teaches that the first liner layer 107 comprises a titanium nitride (TiN) film doped with carbon (C) (see, e.g., pars. 0027-0028, 0078).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0090583) in view of Jang (US 2018/0174845), and further in view of Milligan (US 2017/0025280).
Regarding Claim 19, Choi and Jang teach all aspects of claim 18. They disclose that the liner 107 comprises TiN doped with carbon, hydrogen (see, e.g., pars. 0027-0028, 0078). They do not disclose that the first liner layer comprises a titanium nitride (TiN) film doped with boron (B).
Milligan, on the other hand, teaches a boron-doped TiN layer, to obtain metallic films with high work function and low resistivity (see, e.g., Abstract, par. 0017).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Choi’s process, the TiN film doped with boron (B), as taught by Milligan, to obtain metallic films with high work function and low resistivity.
Response to Arguments
Applicant’s arguments filed on 04/09/2026 with respect to the rejection of claims 1, 14, and 18 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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