DETAILED ACTION
This action is responsive to the application No. 18/522,867 filed on November 29, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 with the associated claims filed on 12/01/2025 responding to the Office action mailed on 10/02/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claim 3 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2016/0020118).
Regarding Claim 1, Park (see, e.g., Figs. 1-9), teaches a method for forming a semiconductor device structure comprising:
providing a substrate 10 comprising a plurality of trenches 30/31, wherein the plurality of trenches 30 comprise at least one NMOS gate trench 31 and at least one PMOS gate trench 30, wherein at least one of the plurality of trenches 30/31 comprises a sidewall and a bottom portion, wherein an interfacial layer 32/33 is disposed on a bottom portion and wherein a spacer 22/23 is disposed on the sidewall (see, e.g., Figs. 2, 3, pars. 0062, 0068);
depositing a gate dielectric 34a/35a over the plurality of trenches 30/31, wherein the gate dielectric 34a/35a is conformally deposited on the spacer 22/23 extending from an opening of the trench 30/31 to the interfacial layer 32/33 (see, e.g., Fig. 3, par. 0071);
depositing a NMOS gate electrode 39a/43a/45a over the plurality of trenches 30/31 such that the NMOS gate electrode 39a/43a/45a spans a surface of the gate dielectric 34a/35a in the plurality of trenches 30/31 (see, e.g., Fig. 7, pars. 0081, 0086, 0089);
removing at least a portion (i.e., portion 39a) of the NMOS gate electrode 39a/43a/45a in the at least one PMOS gate trench 30 (see, e.g., Fig. 6, par. 0082); and
after removing at least a portion of the NMOS gate electrode 39a/43a/45a in the at least one PMOS gate trench 30, depositing a first work function metal 50a/51a in the plurality of trenches 30/31 (see, e.g., Fig. 7, par. 0091),
wherein depositing the NMOS gate electrode 39a/43a/45a comprises:
depositing a first liner layer 39a comprising titanium nitride (see, e.g., par. 0081);
depositing a second work function metal 43a comprising at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), and niobium aluminum carbide (NbAlC) on the first liner layer 39a (see, e.g., par. 0086); and
depositing a second liner layer 45a comprising one or more of titanium nitride, tantalum nitride, or niobium nitride on the second work function metal 43a (see, e.g., par. 0089),
wherein the first work function metal 51a is deposited directly over the second liner layer 45a in the NMOS gate trench 31.
Regarding Claim 8, Park teaches all aspects of claim 1. Park (see, e.g., Figs. 1-9), teaches that removing at least a portion of the NMOS gate electrode 39a/43a/45a in the at least one PMOS gate trench 30 comprises forming a masking layer 1040 in the at least one NMOS gate trench 31 and exposing the substrate 10 to an etchant (see, e.g., par. 0082).
Regarding Claim 11, Park teaches all aspects of claim 1. Park (see, e.g., Figs. 1-9), teaches that the second work function metal 43a comprises at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), or niobium aluminum carbide (NbAlC) (see, e.g., par. 0086).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 18 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 2018/0090583).
Regarding Claim 18, Choi (see, e.g., Figs. 4A-8A), teaches a method for forming a PMOS semiconductor device structure 100 comprising:
providing a substrate 110 comprising at least one trench GH, wherein at least one of the plurality of trenches GH comprises a sidewall and a bottom portion, wherein an interfacial layer 112 is disposed on the bottom portion, wherein a spacer 124 is disposed on the sidewall (see, e.g., Figs. 6A, 7A, pars. 0022, 0026, 0027, 0054);
depositing a gate dielectric 114 over the at least one trench GH, wherein the gate dielectric 114 is conformally deposited on the spacer 124 extending from an opening of the trench GH to the interfacial layer 112 (see, e.g., Fig. 7A, par. 0026);
depositing a first liner layer 115a directly onto the gate dielectric 114 such that the first liner layer 115a spans a surface of the gate dielectric 114 in the plurality of trenches GH (see, e.g., Fig. 7A, par. 0030); and
depositing a first work function metal 115b directly onto the first liner layer 115a, wherein the first work function metal 115b comprises molybdenum (see, e.g., Fig. 7A, pars. 0030-0031).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Choi (US 2018/0090583).
Regarding Claim 2, Park teaches all aspects of claim 1. Park (see, e.g., Figs. 1-9), teaches that the first work function metal 50a/51a comprises aluminum (Al) and/or tungsten (W) (see, e.g., par. 0091). Park does not teach that the first work function metal comprises molybdenum.
Park discloses the claimed invention except for the use of Al and/or W instead of molybdenum (Mo) for the first work function metal (see, e.g., par. 0091). Choi, on the other hand teaches that Al, W, and Mo are equivalent materials known in the art (see, e.g., Choi, Fig. 8A, par. 0031). Therefore, because these work function materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute Al and/or W for Mo since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 14, Park (see, e.g., Figs. 1-9), teaches a method for forming a NMOS semiconductor device structure comprising:
providing a substrate 10 comprising at least one trench 30/31, wherein at least one of the plurality of trenches 30/31 comprises a sidewall and a bottom portion, wherein and interfacial layer 32/33 is disposed on the bottom portion, wherein a spacer 22/23 is disposed on the sidewall (see, e.g., Figs. 2, 3, pars. 0062, 0068);
depositing a gate dielectric 34a/35a over the at least one trench 30/31, wherein the gate dielectric 34a/35a is conformally deposited on the spacer 22/23 extending from an opening of the trench 30/31 to the interfacial layer 32/33 (see, e.g., Fig. 3, par. 0071);
depositing a NMOS gate electrode 39a/43a/45a such that the NMOS gate electrode 39a/43a/45a spans a surface of the gate dielectric 34a/35a in the plurality of trenches 30/31 (see, e.g., Fig. 7, pars. 0081, 0086, 0089); and
depositing a first work function metal 50a/51a in the at least one trench 30/31 (see, e.g., Fig. 7, par. 0090),
wherein depositing the NMOS gate electrode 39a/43a/45a comprises:
depositing a first liner layer 39a comprising titanium nitride (see, e.g., par. 0081);
depositing a second work function metal 43a comprising at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), and niobium aluminum carbide (NbAlC) (see, e.g., par. 0086), and
depositing a second liner layer 45a comprising one or more of titanium nitride, tantalum nitride, or niobium nitride (see, e.g., par. 0089),
wherein the first work function metal 51a is deposited directly over the second liner layer 45a.
Park is silent with respect to the claim limitation that the first work function metal 50a/51a comprises molybdenum.
Park discloses the claimed invention except for the use of Al and/or W instead of molybdenum (Mo) for the first work function metal (see, e.g., par. 0091). Choi, on the other hand teaches that Al, W, and Mo are equivalent materials known in the art (see, e.g., Choi, Fig. 8A, par. 0031). Therefore, because these work function materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute Al and/or W for Mo since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 16, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches that the second liner layer 45a comprises tantalum nitride or niobium nitride (see, e.g., par. 0089).
Regarding Claim 17, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches that the second work function metal 43a comprises at least one of titanium carbide (TiC), tantalum carbide, titanium aluminum carbide (TiAlC), or niobium aluminum carbide (NbAlC) (see, e.g., par. 0086).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Sung (US 2016/0042954).
Regarding Claim 4, Park teaches all aspects of claim 1. Park does not teach that the step of removing at least a portion of the NMOS gate electrode comprises removing the second liner layer, the second work function metal, and at least a portion of the first liner layer in the at least one PMOS gate trench.
Sung (see, e.g., Figs. 4A-4J), in similar fabrication processes to Park, on the other hand, teaches that the step of removing at least a portion of the NMOS gate electrode 430/444/414 comprises removing the second liner layer 430, the second work function metal 444, and at least a portion of the first liner layer 414 in the at least one PMOS gate trench 412, in order to achieve the desired work function, and thus enable a desired threshold voltage of the PFETs and NFETs transistors (see, e.g., Fig. 4G, pars. 0003, 0107).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Park’s process, the step of removing at least a portion of the NMOS gate electrode comprising removing the second liner layer, the second work function metal, and at least a portion of the first liner layer in the at least one PMOS gate trench, as taught by Sung, in order to achieve the desired work function, and thus enable a desired threshold voltage of the PFETs and NFETs transistors.
Regarding Claim 5, Park and Sung teach all aspects of claim 4. Sung (see, e.g., Figs. 4A-4J), teaches depositing a third liner layer 447 after removing at least a portion of the first liner layer 414 in the at least one PMOS gate trench 412 and before depositing a first work function metal 437 (see, e.g., Figs. 4i, 4J, pars. 0109-0110).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Wang (US 2018/0175201).
Regarding Claim 6, Park teaches all aspects of claim 1. Park is silent with respect to the claim limitation that depositing the gate dielectric 34a/35a comprises a chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) process. Wang (see, e.g., Fig. 9), in similar processes to Park, on the other hand, teaches that to achieve a conformal layer, the gate dielectric 56 is deposited by a PECVD process and the like (see, e.g., par. 0022).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the gate dielectric in Park’s process by a chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) process, as taught by Wang, to achieve a conformal layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Bao (US 2018/0315756).
Regarding Claim 7, Park teaches all aspects of claim 1. Park does not teach that depositing the first work function metal 50a/51a comprises a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.
Bao, in similar processes to Park, on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033).
It would have been obvious to one of ordinary skill in the art at the time of filing to include an atomic layer deposition process in the method of Park, as taught by Bao, to deposit a conformal metal gate.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Seung Park (US 9,275,834).
Regarding Claim 9, Park teaches all aspects of claim 8. Park is silent with respect to the claim limitation that the etchant comprises at least one of sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or nitrogen trifluoride (NF3).
Seung Park, on the other hand, teaches selectively etching TiN layers relative to metals/conductors, using NF3, SF6 to assist in removing oxidation (if present) on the titanium nitride and to avoid the formation of pits on the surfaces of some materials (see, e.g., col. 3, ll. 21-24, 54-63, col. 5, ll. 35-55).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Park’s process an etchant comprising at least one of sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or nitrogen trifluoride (NF3), as taught by Seung Park, to assist in removing oxidation (if present) on the titanium nitride and to avoid the formation of pits on the surfaces of some materials.
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Bao (US 2018/0315756) and further in view of Xiao (US 2017/0226636).
Regarding Claim 10, Park teaches all aspects of claim 1. Park (see, e.g., Figs. 1-9), teaches depositing a first work function metal 50a/51a (see, e.g., par. 0090).
Park is silent with respect to the claim limitations that depositing the first work function metal comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
Bao on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033), and Xiao, teaches contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor that is capable of reacting with the metal containing precursor to produce metal crystal growth on a heated surface (see, e.g., Xiao, pars. 0004, 0035).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the first work function metal comprising an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor, as taught by Bao and Xiao, to deposit a conformal molybdenum metal gate on a heated surface.
Regarding Claim 12, Park, Bao, and Xiao teach all aspects of claim 10. Xiao teaches that the molybdenum precursor comprises at least one of molybdenum pentachloride (MoCl5) or molybdenum dichloride dioxide (MoO2Cl2) (see, e.g., par. 0035).
Regarding Claim 13, Park, Bao, and Xiao teach all aspects of claim 10. Xiao teaches that the reducing agent precursor comprises hydrogen (H2) (see, e.g., par. 0035).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0020118) in view of Choi (US 2018/0090583) and further in view of Bao (US 2018/0315756) and Xiao (US 2017/0226636).
Regarding Claim 15, Park and Choi teach all aspects of claim 14. Park (see, e.g., Figs. 1-9), teaches depositing a first work function metal 50a/51a (see, e.g., par. 0090).
Park is silent with respect to the claim limitations that depositing the first work function metal comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
Bao on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033), and Xiao, teaches contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor that is capable of reacting with the metal containing precursor to produce metal crystal growth on a heated surface (see, e.g., Xiao, pars. 0004, 0035).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the first work function metal comprising an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor, as taught by Bao and Xiao, to deposit a conformal molybdenum metal gate on a heated surface.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0090583) in view of Bao (US 2018/0315756) and Xiao (US 2017/0226636).
Regarding Claim 19, Choi teaches all aspects of claim 18. Choi (see, e.g., Figs. 4A-8A), teaches depositing a molybdenum first work function metal 115b by an ALD process (see, e.g., pars. 0031, 0058).
Choi is silent with respect to the claim limitations that depositing the first work function metal comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
Bao on the other hand, teaches using an atomic layer deposition process to deposit a conformal molybdenum metal gate (see, e.g., Bao, par. 0033), and Xiao, teaches contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor that is capable of reacting with the metal containing precursor to produce metal crystal growth on a heated surface (see, e.g., Xiao, pars. 0004, 0035).
It would have been obvious to one of ordinary skill in the art at the time of filing to deposit the first work function metal comprising an atomic layer deposition process, wherein the atomic layer deposition process comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor, as taught by Bao and Xiao, to deposit a conformal molybdenum metal gate on a heated surface.
Regarding Claim 20, Choi, Bao, and Xiao teach all aspects of claim 19. Xiao teaches that the molybdenum precursor comprises at least one of molybdenum pentachloride (MoCl5) or molybdenum dichloride dioxide (MoO2Cl2) (see, e.g., par. 0035).
Response to Arguments
Applicant’s arguments filed on 12/01/2025 with respect to the rejection of claims 1, 14, and 18 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814