DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-6 and 10-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6140175 (Kleinhenz et al).
Concerning claim 1, Kleinhenz discloses a semiconductor device (Figs. 1-18), comprising:
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a substrate (11) (Fig. 1); an active region (181) in the substrate (col. 5 lines 34-40); a gate structure in the active region (Fig. 18), the gate structure comprising a bottom conductive layer (13) (Fig. 18 and col. 4 lines 6-10), a top conductive layer (100) on the bottom conductive layer (Fig. 18 and col. 4 lines 62-67), and a cap layer (150) on the top conductive layer (Fig. 18 and col. 5 lines 13-23), wherein a width of the bottom conductive layer is wider than a width of the top conductive layer, and a width of the cap layer is wider than the width of the top conductive layer (Fig. 18, note that feature 90 is formed on the sidewalls of feature 100 (top conductive layer) and the upper surface of the bottom conductive layer and they restrict the overall width of the feature and therefore the width of the top conductive layer is smaller than the width of the bottom conductive layer. The width of the cap layer extends beyond the sidewall of the top conductive layer leading to the cap layer having a width larger than the underlying top conductive layer), wherein the top conductive layer and the bottom conductive layer are made of a same material (col. 4 lines 6-10 and 62-67, it is disclosed that the material of the top and bottom conductive layers are made of doped polysilicon), and a passivation layer (90, col. 4 lines 51-54) surrounding the top conductive layer, wherein a bottom surface of the cap layer is in direct contact with a top surface of the top conductive layer and a part of a top surface of the passivation layer (annotated Fig. 18 above shows two rectangular regions, the top rectangularly enclosed region shows the bottom surface of the cap layer in direct contact with a top surface of the top conductive layer and the bottom rectangularly enclosed region shows the bottom surface of the cap layer in direct contact with a top surface of the passivation layer).
Regarding claim 2, Kleinhenz discloses wherein a work function of the top conductive layer is identical to a work function of the bottom conductive layer (col. 4 lines 6-10 and 62-67).
Referring to claim 4, Kleinhenz discloses wherein a material of the cap layer comprises silicon nitride (col. 4 lines 51-54).
Considering claim 5, Kleinhenz discloses wherein an interface is present between the bottom conductive layer and the top conductive layer (Fig. 18 and col. 4 lines 51-61).
Continuing to claim 6, Kleinhenz discloses a lining layer (20) surrounding the bottom conductive layer (col. 4 lines 13-24), wherein a thickness of the passivation layer is thicker than a thickness of the lining layer (Fig. 3 and Fig. 10).
Pertaining to claim 10, Kleinhenz discloses a method of forming a semiconductor device, the method comprising:
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forming an active region (181) in a substrate (11) (Fig. 18 and col. 5 lines 34-40); forming a trench (13) in the active region (Fig. 1); depositing a lining layer (20) in the trench (Fig. 2 and col. 4 lines 4-8); depositing a conductive material (21) to fill the trench (Fig. 2); etching back the conductive material and the lining layer to form a bottom conductive layer (21) in the trench (Figs. 3 and 4); and forming a top conductive layer (100) on the bottom conductive layer (Fig. 10 and col. 4 lines 62-67), comprising depositing a passivation layer (90) on the bottom conductive layer and on a sidewall of the trench (Fig. 9); depositing a cap material (150) to fill the trench and above the substrate; and removing a portion of the cap material to form a cap layer on the top conductive layer (col. 5 lines 13-24) ; wherein a bottom surface of the cap layer is in direct contact with a top surface of the top conductive layer and a part of a top surface of the passivation layer (annotated Fig. 18 above shows two rectangular regions, the top rectangularly enclosed region shows the bottom surface of the cap layer in direct contact with a top surface of the top conductive layer and the bottom rectangularly enclosed region shows the bottom surface of the cap layer in direct contact with a top surface of the passivation layer) wherein a width of the bottom conductive layer is wider than a width of the top conductive layer (Fig. 18, note that feature 90 is formed on the sidewalls of feature 100 (top conductive layer) and the upper surface of the bottom conductive layer and they restrict the overall width of the feature and therefore the width of the top conductive layer is smaller than the width of the bottom conductive layer. The width of the cap layer extends beyond the sidewall of the top conductive layer leading to the cap layer having a width larger than the underlying top conductive layer), and the top conductive layer and the bottom conductive layer are made of a same material ([0044] and [0049], it is noted that it is disclosed that the material of the top and bottom conductive layer can be the same material. The examiner is interpreting that material to be TiN).
As to claim 11, Kleinhenz discloses wherein the top conductive layer is directly in contact with the bottom conductive layer (Fig. 18), and an interface is present between the top conductive layer and the bottom conductive layer (Fig. 18 and col. 4 lines 51-61).
Concerning claim 12, Kleinhenz discloses wherein a thin portion of the lining layer is remained on a sidewall of the trench after etching back the conductive material and the lining layer (col. 4 lines 14-26).
Regarding claim 13, Kleinhenz discloses wherein forming the top conductive layer on the bottom conductive layer comprises (Figs. 8-12): depositing a passivation layer (90) on the bottom conductive layer and on a sidewall of the trench (Fig. 9); removing a lateral portion of the passivation layer to expose a top surface of the bottom conductive layer (Fig. 9); depositing an additional conductive material (100) to fill the trench (Fig. 10 and col. 4 lines 62-67); and etching back the additional conductive material and the passivation layer such that the top conductive layer is formed on the bottom conductive layer (Figs. 11-12).
Pertaining to claim 14, Kleinhenz discloses wherein a thickness of the passivation layer is thicker than a thickness of the lining layer (Fig. 3 and Fig. 10).
As to claim 15, Kleinhenz discloses wherein an edge of the top surface of the bottom conductive layer is covered by the passivation layer (Fig. 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20140061781 (Kim).
Pertaining to claim 3, Kleinhenz discloses using a conductive material for the top and bottom conductive layer.
Kleinhenz does not disclose wherein the material of the bottom conductive layer and the top conductive layer comprise titanium nitride. However, Kim discloses an analogous semiconductor device in which a material of the gate (conductive material) is disclosed as being TiN ([0044]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use TiN as the material of the top and bottom conductive layer because are known suitable materials in the art for gate (conductive) material layers.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20230402518 (Park et al).
Continuing to claim 7, Kleinhenz discloses forming the top conductive layer.
Kleinhenz does not disclose further comprising: a passivation layer surrounding the top conductive layer; and a barrier layer surrounding the cap layer, wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer. However, Park discloses a semiconductor device (Figs. 12-17 and [0106]-[0120]) with a trench gate configuration with a bottom conductive layer (124a) a top conductive layer (124b) and a gate capping layer (126). Park discloses a passivation layer (122b) surrounding the top conductive layer; and a barrier layer (122b) surrounding the cap layer (Fig. 16), wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer (Figs. 16 and 17). Park discloses a base insulating layer formed between the liner insulating layer and the gate electrode structure and a reinforcing insulating layer formed on the sidewall portion of the second sub-gate electrode and including a silicon oxide layer, wherein a second thickness of the reinforcing insulating layer and the base insulating layer formed on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer formed on the sidewall portion of the gate capping layer on a bottom level of the gate capping layer and that such configuration is adapted to improve the reliability of a gate insulating layer provided on a gate electrode structure in order to prevent degradation of the reliability of the gate insulating which may lead to deterioration of the operating performance of the IC devices ([0003] and [0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kleinhenz in order to provide a barrier layer surrounding the cap layer with a thickness less than the thickness of the passivation surrounding the top conductive layer as disclosed by Park in order to improve the reliability of the gate insulating layer and prevent deterioration of the operating performance of the device.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20200203351 (Chae et al)).
As to claim 8, Kleinhenz discloses forming the semiconductor device (Figs. 1-18).
Kleinhenz does not disclose further comprising: an isolation region in the substrate, and a dummy gate structure in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate. However, Chae discloses a semiconductor device configuration (Fig. 3) in which an isolation region (120) is formed in a substrate (110) (Fig. 3 and [0026]) and a dummy gate (WL2) in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate (Fig. 3). Chae discloses that this configuration provides a memory device having improved electrical characteristics ([0004]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Kleinhenz to include an isolation region in the substrate and a dummy gate structure in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate as disclosed by Chae in order to provide a memory device with improved electrical characteristics.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20200203351 (Chae et al) as applied to claim 8 above, and further in view of US 20200243375 (Kang et al).
Concerning claim 9, Kleinhenz in view of Chae discloses wherein the isolation region comprises an oxide layer (Chae [0026]).
Kleinhenz in view of Chae does not disclose the isolation region is directly in contact with the active region and a nitride layer sandwiched by the oxide layer. However, Kang discloses an isolation material configuration (116) (Fig. 3C) in which an oxide layer (116A) is in direct contact with an active region and a nitride layer (116B) is sandwiched by the oxide layer (Fig. 3C and [0025]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the isolation structure of Kleinhenz in view of Chae such that the isolation region comprises an oxide layer that is directly in contact with the active region with a nitride layer sandwiched because such material configuration is known in the art to be suitable for an isolation structure as disclosed by Kang.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20040021163 (Bonart et al).
Concerning claim 16, Kleinhenz discloses forming the passivation layer and top conductive layer and etching back both structures (Fig. 12).
Kleinhenz does not disclose wherein a thin portion of the passivation layer is remained on the sidewall of the trench after etching back the additional conductive material and the passivation layer. However Bonart discloses an analogous semiconductor device configuration in which a thin portion of the passivation layer is remained on the sidewall of the trench after etching back the additional conductive material and the passivation layer (Fig. 2 and [0032]) and that such process steps enables a comparatively simple process implementation in conjunction with improved process control ([0005]).Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the process of Kleinhenz in order to leave a thin portion of the passivation layer after the recessing of the top conductive layer as disclosed by Bonart for improved process control.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6140175 (Kleinhenz et al) in view of US 20230402518 (Park et al).
Considering claim 17, Kleinhenz discloses forming a top conductive layer and a capping layer.
Kleinhenz does not disclose depositing a barrier layer on the top conductive layer and on the sidewall of the trench; removing a lateral portion of the barrier layer to expose a top surface of the top conductive layer; depositing a cap material to fill the trench and above the substrate; and removing a portion of the cap material to form a cap layer on the top conductive layer. However, Park discloses a semiconductor device (Figs. 12-17 and [0106]-[0120]) with a trench gate configuration with a bottom conductive layer (124a) a top conductive layer (124b) and a gate capping layer (126). Park discloses depositing a barrier layer (122b) on the top conductive layer and on the sidewall of the trench; removing a lateral portion of the barrier layer to expose a top surface of the top conductive layer ([0111]); depositing a cap material (126) to fill the trench and above the substrate; and removing a portion of the cap material to form a cap layer on the top conductive layer ([0115] and Figs. 16 and 17). Park discloses a base insulating layer formed between the liner insulating layer and the gate electrode structure and a reinforcing insulating layer formed on the sidewall portion of the second sub-gate electrode and including a silicon oxide layer, wherein a second thickness of the reinforcing insulating layer and the base insulating layer formed on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer formed on the sidewall portion of the gate capping layer on a bottom level of the gate capping layer and that such configuration is adapted to improve the reliability of a gate insulating layer provided on a gate electrode structure in order to prevent degradation of the reliability of the gate insulating which may lead to deterioration of the operating performance of the IC devices ([0003] and [0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kleinhenz in order to provide a barrier layer surrounding the cap layer with a thickness less than the thickness of the passivation surrounding the top conductive layer as disclosed by Park in order to improve the reliability of the gate insulating layer and prevent deterioration of the operating performance of the device.
Referring to claim 18, Kleinhenz in view of Park discloses wherein a width of the cap layer is wider than the width of the top conductive layer (Kleinhenz Fig. 18).
Regarding claim 19, Kleinhenz in view of Park discloses wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer (Kleinhenz Fig. 3 and Fig. 10).
Pertaining to claim 20, Kleinhenz in view of Park wherein removing the portion of the cap material comprises performing a planarization process (Kleinhenz col. 5 lines 14-24).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 07/09/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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