DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20140061781 (Kim).
Concerning claim 1, Kim discloses a semiconductor device (Figs. 3A-3H), comprising:
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a substrate (101) (Fig. 3H); an active region (102) in the substrate ([0041] and Fig. 3A); and a gate structure in the active region (Fig. 3H), the gate structure comprising a bottom conductive layer (112/113) (Figs. 3B-3C and [0044]), a top conductive layer (119/121) on the bottom conductive layer (Figs. 3F-3G and [0049]), and a cap layer (140) on the top conductive layer (Fig. 3H and [0051]), wherein a width of the bottom conductive layer is wider than a width of the top conductive layer, and a width of the cap layer is wider than the width of the top conductive layer (Fig. 3H, note that there are two layers formed on the sidewalls of feature 121 (top conductive layer) and the upper surface of the bottom conductive layer and they restrict the overall width of the feature and therefore the width of the top conductive layer is smaller than the width of the bottom conductive layer. Also the two aforementioned layers that are formed on the sidewalls of the top conductive layer are not present between the sidewall surfaces of the cap layer 140 and therefore do not restrict its width leading to the cap layer having a width larger than the underlying top conductive layer), wherein the top conductive layer and the bottom conductive layer are made of a same material ([0044] and [0049], it is noted that it is disclosed that the material of the top and bottom conductive layer can be the same material. The examiner is interpreting that material to be TiN).
Continuing to claim 2, Kim discloses wherein a work function of the top conductive layer is identical to a work function of the bottom conductive layer ([0049]).
Considering claim 3, Kim discloses wherein the material of the bottom conductive layer and the top conductive layer comprises titanium nitride ([0049]).
Referring to claim 4, Kim discloses wherein a material of the cap layer comprises silicon nitride ([0051]).
Regarding claim 5, Kim discloses wherein an interface is present between the bottom conductive layer and the top conductive layer (Fig. 3H).
Pertaining to claim 10, Kim discloses a method of forming a semiconductor device, the method comprising:
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forming an active region (102) in a substrate (101) (Fig. 3A and [0041]); forming a trench (107) in the active region (Fig. 3A and [0041]); depositing a lining layer (111) in the trench (Fig. 3B and [0043]-[0044]); depositing a conductive material (112) to fill the trench (Fig. 3B and [0042]); etching back the conductive material and the lining layer to form a bottom conductive layer (113) in the trench (Fig. 3C and [0045]); and forming a top conductive layer (121) on the bottom conductive layer (Fig. 3G and [0050]), wherein a width of the bottom conductive layer is wider than a width of the top conductive layer (Fig. 3H, note that there are two layers formed on the sidewalls of feature 121 (top conductive layer) and the upper surface of the bottom conductive layer and they restrict the overall width of the feature and therefore the width of the top conductive layer is smaller than the width of the bottom conductive layer. Also the two aforementioned layers that are formed on the sidewalls of the top conductive layer are not present between the sidewall surfaces of the cap layer 140 and therefore do not restrict its width leading to the cap layer having a width larger than the underlying top conductive layer), and the top conductive layer and the bottom conductive layer are made of a same material ([0044] and [0049], it is noted that it is disclosed that the material of the top and bottom conductive layer can be the same material. The examiner is interpreting that material to be TiN).
As to claim 11, Kim discloses wherein the top conductive layer is directly in contact with the bottom conductive layer (Fig. 3F and 3G), and an interface is present between the top conductive layer and the bottom conductive layer (Fig. 3G and [0049]-[0050]).
Concerning claim 12, Kim discloses wherein a thin portion of the lining layer is remained on a sidewall of the trench after etching back the conductive material and the lining layer (Fig. 3C, note that the lining layer is still present between the bottom conductive layer and the sidewalls of the trench structure).
Claim(s) 1, 6, 10, and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 5399516 (Bergendahl et al).
Continuing to claim 1, Bergendahl discloses a semiconductor device, comprising:
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a substrate (13 and 16) (Fig. 5); an active region (Region shown in Fig. 5) in the substrate; and a gate structure in the active region (Fig. 5), the gate structure comprising a bottom conductive layer (18) (Figs. 3b and 5 and col. 9 lines 19-22), a top conductive layer (6) on the bottom conductive layer (Fig. 5 and col. 10 lines 46-50), and a cap layer (22) on the top conductive layer (Fig. 5 and col. 10 lines 53-57), wherein a width of the bottom conductive layer is wider than a width of the top conductive layer, and a width of the cap layer is wider than the width of the top conductive layer (Fig. 5), wherein the top conductive layer and the bottom conductive layer are made of a same material (col. 9 lines 19-22 and col. 10 lines 46-50, note that the same material these features are made of is disclosed to be polysilicon).
Considering claim 6, Bergendahl discloses further comprising: a lining layer (8) surrounding the bottom conductive layer (col. 8 lines 35-40); and a passivation layer (7) surrounding the top conductive layer (Fig. 5), wherein a thickness of the passivation layer is thicker than a thickness of the lining layer (col. 9 lines 16-18 and col. 10 lines 12-36. The thickness of lining layer is disclosed to be 300 Å and the thickness of the passivation layer is disclosed to consist of three layers with the first layer being 200 Å, the second layer being (on the lower end of the range) 50 Å, and the third layer being 200 Å for a total thickness of 450 Å which is thicker than the lining layer).
Referring to claim 10, Bergendahl discloses a method of forming a semiconductor device, the method comprising (Figs. 2b-5):
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forming an active region in a substrate (Fig. 2b); forming a trench in the active region (Fig. 3b); depositing a lining layer (8) in the trench (col. 8 lines 35-40); depositing a conductive material (18) to fill the trench (Figs. 3b and 5 and col. 9 lines 19-22); etching back the conductive material and the lining layer to form a bottom conductive layer in the trench (Figs. 3b and 5 and col. 9 lines 19-22); and forming a top conductive layer (6) on the bottom conductive layer, wherein a width of the bottom conductive layer is wider than a width of the top conductive layer (Fig. 5 and col. 10 lines 46-50), and the top conductive layer and the bottom conductive layer are made of a same material (col. 9 lines 19-22 and col. 10 lines 46-50, note that the same material these features are made of is disclosed to be polysilicon).
Regarding claim 13, Bergendahl discloses wherein forming the top conductive layer on the bottom conductive layer comprises (Fig. 5): depositing a passivation layer (7 +19) on the bottom conductive layer and on a sidewall of the trench (col. 10 lines 12-36); removing a lateral portion of the passivation layer to expose a top surface of the bottom conductive layer (col. 10 lines 42-45, note that a portion of the lateral passivation layer 19 is removed such that the top conductive layer is in direct contact with the bottom conductive layer); depositing an additional conductive material (6) to fill the trench (Fig. 5 and col. 10 lines 45-50); and etching back the additional conductive material and the passivation layer such that the top conductive layer is formed on the bottom conductive layer (Fig. 5 and col. 10 lines 45-50).
Pertaining to claim 14, Bergendahl discloses wherein a thickness of the passivation layer is thicker than a thickness of the lining layer (col. 9 lines 16-18 and col. 10 lines 12-36. The thickness of lining layer is disclosed to be 300 Å and the thickness of the passivation layer is disclosed to consist of three layers with the first layer being 200 Å, the second layer being (on the lower end of the range) 50 Å, and the third layer being 200 Å for a total thickness of 450 Å which is thicker than the lining layer).
As to claim 15, Bergendahl discloses wherein an edge of the top surface of the bottom conductive layer is covered by the passivation layer (Fig. 5, note that the top edges of bottom conductive layer are covered by portions 19 of the passivation layer).
Concerning claim 16, Bergendahl discloses wherein a thin portion of the passivation layer is remained on the sidewall of the trench after etching back the additional conductive material and the passivation layer (Fig. 5 and col. 10 lines 42-50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140061781 (Kim) in view of US 20230402518 (Park et al).
Continuing to claim 7, Kim discloses forming the top conductive layer.
Kim does not disclose further comprising: a passivation layer surrounding the top conductive layer; and a barrier layer surrounding the cap layer, wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer. However, Park discloses a semiconductor device (Figs. 12-17 and [0106]-[0120]) with a trench gate configuration with a bottom conductive layer (124a) a top conductive layer (124b) and a gate capping layer (126). Park discloses a passivation layer (122b) surrounding the top conductive layer; and a barrier layer (122b) surrounding the cap layer (Fig. 16), wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer (Figs. 16 and 17). Park discloses a base insulating layer formed between the liner insulating layer and the gate electrode structure and a reinforcing insulating layer formed on the sidewall portion of the second sub-gate electrode and including a silicon oxide layer, wherein a second thickness of the reinforcing insulating layer and the base insulating layer formed on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer formed on the sidewall portion of the gate capping layer on a bottom level of the gate capping layer and that such configuration is adapted to improve the reliability of a gate insulating layer provided on a gate electrode structure in order to prevent degradation of the reliability of the gate insulating which may lead to deterioration of the operating performance of the IC devices ([0003] and [0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kim in order to provide a barrier layer surrounding the cap layer with a thickness less than the thickness of the passivation surrounding the top conductive layer as disclosed by Park in order to improve the reliability of the gate insulating layer and prevent deterioration of the operating performance of the device.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140061781 (Kim) in view of US 20200203351 (Chae et al)).
As to claim 8, Kim discloses further comprising: an isolation region in the substrate ([0035] and [0041]).
Kim does not disclose a dummy gate structure in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate. However, Chae discloses a semiconductor device configuration (Fig. 3) in which an isolation region (120) is formed in a substrate (110) (Fig. 3 and [0026]) and a dummy gate (WL2) in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate (Fig. 3). Chae discloses that this configuration provides a memory device having improved electrical characteristics ([0004]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Kim to include a dummy gate structure in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate as disclosed by Chae in order to provide a memory device with improved electrical characteristics.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140061781 (Kim) in view of US 20200203351 (Chae et al) as applied to claim 8 above, and further in view of US 20200243375 (Kang et al).
Concerning claim 9, Kim in view of Chae discloses wherein the isolation region comprises an oxide layer (Chae [0026]).
Kim in view of Chae does not disclose the isolation region is directly in contact with the active region and a nitride layer sandwiched by the oxide layer. However, Kang discloses an isolation material configuration (116) (Fig. 3C) in which an oxide layer (116A) is in direct contact with an active region and a nitride layer (116B) is sandwiched by the oxide layer (Fig. 3C and [0025]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the isolation structure of Kim in view of Chae such that the isolation region comprises an oxide layer that is directly in contact with the active region with a nitride layer sandwiched because such material configuration is known in the art to be suitable for an isolation structure as disclosed by Kang.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 5399516 (Bergendahl et al) in view of US 20230402518 (Park et al).
Considering claim 17, Bergendahl discloses forming a top conductive layer and a capping layer.
Bergendahl does not disclose depositing a barrier layer on the top conductive layer and on the sidewall of the trench; removing a lateral portion of the barrier layer to expose a top surface of the top conductive layer; depositing a cap material to fill the trench and above the substrate; and removing a portion of the cap material to form a cap layer on the top conductive layer. However, Park discloses a semiconductor device (Figs. 12-17 and [0106]-[0120]) with a trench gate configuration with a bottom conductive layer (124a) a top conductive layer (124b) and a gate capping layer (126). Park discloses depositing a barrier layer (122b) on the top conductive layer and on the sidewall of the trench; removing a lateral portion of the barrier layer to expose a top surface of the top conductive layer ([0111]); depositing a cap material (126) to fill the trench and above the substrate; and removing a portion of the cap material to form a cap layer on the top conductive layer ([0115] and Figs. 16 and 17). Park discloses a base insulating layer formed between the liner insulating layer and the gate electrode structure and a reinforcing insulating layer formed on the sidewall portion of the second sub-gate electrode and including a silicon oxide layer, wherein a second thickness of the reinforcing insulating layer and the base insulating layer formed on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer formed on the sidewall portion of the gate capping layer on a bottom level of the gate capping layer and that such configuration is adapted to improve the reliability of a gate insulating layer provided on a gate electrode structure in order to prevent degradation of the reliability of the gate insulating which may lead to deterioration of the operating performance of the IC devices ([0003] and [0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kim in order to provide a barrier layer surrounding the cap layer with a thickness less than the thickness of the passivation surrounding the top conductive layer as disclosed by Park in order to improve the reliability of the gate insulating layer and prevent deterioration of the operating performance of the device.
Referring to claim 18, Bergendahl in view of Park discloses wherein a width of the cap layer is wider than the width of the top conductive layer (Park Figs. 16 and 17).
Regarding claim 19, Bergendahl in view of Park discloses wherein a thickness of the passivation layer is thicker than a thickness of the barrier layer (Park [0007] and [0120]).
Pertaining to claim 20, Bergendahl in view of Park wherein removing the portion of the cap material comprises performing a planarization process (Park [0115]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20110180868 discloses a semiconductor device with a top and bottom conductive layer formed in a trench in a substrate (Fig. 2d).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 01/21/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897