Prosecution Insights
Last updated: May 29, 2026
Application No. 18/523,178

Source Tuning With Pulsed DC Bias

Final Rejection §102
Filed
Nov 29, 2023
Examiner
SATHIRAJU, SRINIVAS
Art Unit
2844
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mks Inc.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
723 granted / 814 resolved
+20.8% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
29 currently pending
Career history
840
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
63.9%
+23.9% vs TC avg
§102
9.6%
-30.4% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102
Notice of Final Rejection Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed on 10/23/2025 have been fully considered but they are not persuasive. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. In the present context, applicant argues that Koshimizu does not teach or suggest the emphasized feature, “Controller configured to generate an impedance control signal to control an impedance between the power source and the load, the atleast one controller further configured to generate the impedance control signal in response to a pulsed DC output signa from second power source.” Examiner respectfully disagrees with applicant’s arguments. Applicant’ depends on paragraph [0057] o mainly and variable DC power supply 50 and continues arguments only on paragraph [0057]. Even though rejection depends on Fig 1, Fig 3 paragraphs [0059] [0057] [0073]. Also, in the conclusion of the office action it was clearly mentioned paragraph 35 of previous office action (dated 08/06/2025) page 11, that applicants are directed to consider additional pertinent prior art included on the notice of references cited PTOL 892 attached here with. The examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicants. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim other passages and figures may apply. Applicant, in preparing the response should consider fully the entire reference as potentially teaching all or part of the claimed invention as well as the context of the passage as taught by the prior art or disclosed by the examiner. However, Fig 1/Fig 2 or Fig 3 or Fig 5 of instant application teaches different ways to control the plasma processing. However, to avoid piece meal prosecution examiner has applied the best reference possible. Applicant conveniently pick and choose the paragraphs to defend his statements. Hence, applicant’s arguments are moot and clarity is provided in the present rejection. Examiner is using the same reference and sticking to the same 35 USC 102 (a) (1) rejection using US 2021-0327681 A1 by Koshimizu et al (Koshimizu). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-29 are rejected under 35 U.S.C. 102(a)(1) as anticipated by US2021-0327681 A1 by Koshimizu et al (Koshimizu). Referring to claim 1 Koshimizu teaches: A RF generator (Fig 1 item 1 RF plasma generator ( paragraphs [0057] -[0059] ) comprising: a power source ( Fig 2A that outputs a time- varying signal to a load (see at least one controller (Fig 1 item 200 controller [0064]) coupled to the power source (See paragraphs [0059]), the at least one controller (item 200) configured to generate an impedance control signal to control an impedance between the power source and the load (See paragraphs [0058] –[0059] where Koshimizu teaches that controller is coupled via matching unit 46 to power supplies 48, 90, which is configured to generate a signal in response to HF/LF power having a Low Frequency RF power supply 48 for assisting the matching units and a load impedance with each other and load), the at least one controller (200) further configured to generate the impedance control signal in response to a pulsed DC output signal from a second power source (See paragraph [0058] , [0059], [0064] [0073]). Referring to the claim 2 Koshimizu teaches the RF generator of claim 1, wherein pulsed DC output signal has a plurality of half cycles, and the impedance control signal varies in accordance with at least one of the plurality of half cycles (See controller 200 transmits a signal to HF RF power supply and varies a frequency of HF power so as to assist a matching unit 88 that is configured to match an internal impedance of the LF RF power supply within a load impedance by adjusting an inductance and a capacitance see paragraphs [0059]-[0073] and also [0136] and claims 1-4 and Fig 1-3). Referring to the claim 3 Koshimizu teaches the RF generator of claim 1, wherein the impedance control signal varies at least one of a frequency of the time- varying signal or an actuator command to a matching network. (see Fig 1-3 and paragraphs [0058] - [0071] claims 1-4). Referring to the claim 4 Koshimizu teaches the RF generator of claim 3, wherein the actuator command varies elements of a matching network, including at least one reactive element. (see Fig 1-3 and paragraphs [0058] - [0071] claims 1-4). Referring to the claim 5 Koshimizu teaches the RF generator of claim 1, wherein the pulsed DC output signal includes a plurality of half cycles, including a negative half cycle and a positive half cycle, and wherein the impedance control signal controls the impedance over the negative half cycle. (See Fig 1-3 and [0059]-[0071]) Referring to the claim 6 Koshimizu teaches the RF generator of claim 5, wherein the negative half cycle has a duration longer than the positive half cycle. (See Fig 1-4C and paragraphs [0073] -[0099]). Referring to the claim 7 Koshimizu teaches the RF generator of claim 1, wherein pulsed DC output signal includes a plurality of half cycles, including a negative half cycle and a positive half cycle, and wherein the impedance control signal commands a first frequency of the time-varying signal during at least a portion of the negative half cycle. (See Fig 1-3 paragraphs [0087] [0136]-[0138] claim1 ) Referring to the claim 8 Koshimizu teaches the RF generator of claim 7, wherein the impedance control signal commands a second frequency of the time-varying signal during at least a portion of the positive half cycle. (See Fig 1-3 paragraphs [0087] [0136]-[0138] claim1 ). Referring to the claim 9 Koshimizu teaches the RF generator of claim 7, wherein the negative half cycle has a duration longer than the positive half cycle. (See Fig 1-4C and paragraphs [0073] -[0099]). Referring to the claim 10 Koshimizu teaches the RF generator of claim 1, wherein the pulsed DC output signal is modulated by an envelope signal including a plurality of states, and wherein the at least one controller includes a first impedance tuner configured to determine the impedance control signal for a first of the plurality of states and the at least one controller includes a second impedance tuner configured to determine the impedance control signal for a second of the plurality of states. (See paragraphs [0087] [0172] claims 1-4 and Fig 1-4C and 15A=D). Referring to the claim 11 Koshimizu teaches the RF generator of claim 1 wherein the impedance control signal varies a frequency of the time-varying signal using frequency hopping over a plurality of bins over at least a portion of the pulsed DC output signal. (See paragraphs [0087] -[0106] claims 1-4 Fig 1-4C). Referring to the claim 12 Koshimizu teaches; A controller (Fig 1 item 200 paragraph [0058]) for a power generator (item 90+48 RF power supply) comprising: an impedance tuner (item 88+46 matching units see paragraphs [0058], [0059] [0064]) coupled to a power source (item 90+88) that outputs a time-varying signal to a load (See Fig 3 and paragraph [0073]), the impedance tuner (88+46) configured to generate an impedance control signal to control an impedance match between the power source and the load (See paragraph [0058 and [0059], the impedance tuner further configured to generate the impedance control signal in response to a pulsed DC output signal from a second power source (See paragraph [0057] and Fig 3 and paragraph [0073]). Referring to the claim 13 Koshimizu teaches the controller of claim 12, wherein the pulsed DC output signal has a plurality of half cycles, and the impedance control signal varies in accordance with at least one of the plurality of half cycles. (See controller 200 transmits a signal to HF RF power supply and varies a frequency of HF power so as to assist a matching unit 88 that is configured to match an internal impedance of the LF RF power supply within a load impedance by adjusting an inductance and a capacitance see paragraphs [0059]-[0071] and also [0136] and claims 1-4 and Fig 1-3). Referring to the claim 14 Koshimizu teaches the controller of claim 12, wherein the impedance control signal varies at least one of a frequency of the time-varying signal or an actuator command to a matching network. (see Fig 1-3 and paragraphs [0059] - [0071] claims 1-4). Referring to the claim 15 Koshimizu teaches the controller of claim 14, wherein the actuator command varies elements of a matching network, including at least one reactive element. (see Fig 1-3 and paragraphs [0059] - [0071] claims 1-4). Referring to the claim 16 Koshimizu teaches the controller of claim 12, wherein the pulsed DC output signal has a plurality of half cycles, including a negative half cycle and a positive half cycle, and wherein the impedance control signal controls the impedance match over the negative half cycle and does not control the impedance match over the positive half cycle. (See Paragraphs [0073] [0087], [0136] -[0138] and Fig 1-3). Referring to the claim 17 Koshimizu teaches the controller of claim 16, wherein the negative half cycle has a duration longer than the positive half cycle. (See Fig 1-4C and paragraphs [0073] -[0099]). Referring to the claim 18 Koshimizu teaches the controller of claim 12, wherein the pulsed DC output signal has a plurality of half cycles, including a negative half cycle and a positive half cycle, and wherein the impedance control signal commands a first frequency of the time-varying signal during at least a portion of the negative half cycle. (See Fig 1-3 paragraphs [0087] [0136]-[0138] claim1). Referring to the claim 19 Koshimizu teaches the controller of claim 18, wherein the impedance control signal commands a second frequency of the time-varying signal during at least a portion of the positive half cycle. (See Fig 1-3 paragraphs [0087] [0136]- [0138] claim1). Referring to the claim 20 Koshimizu teaches the controller of claim 18, wherein the negative half cycle has a duration longer than the positive half cycle. (See Fig 1-4C and paragraphs [0073] -[0099]). Referring to the claim 21 Koshimizu teaches the controller of claim 12, wherein the pulsed DC output signal has a plurality of half cycles, and wherein the impedance tuner includes a first tuner configured to determine the impedance control signal for a first of the plurality of half cycles and the impedance tuner includes a second tuner configured to determine the impedance control signal for a second of the plurality of half cycles (See Fig 1-4C and 15A-D and paragraphs [0073], [0087] and [0172]). Referring to the claim 22 Koshimizu teaches the controller of claim 12 wherein the impedance control signal varies a frequency of the time-varying signal using frequency hopping over a plurality of bins over at least a portion of the pulsed DC output signal. (See an LF/HF power generated from a RF power supply includes a negative half cycle and a positive half cycle and a signal generated from a controller 200 for impedance matching of another DC power source connected to upper electrode and a portion of the pulsed DC cycle signal paragraphs [0087]-[0106]). Referring to the claim 23 Koshimizu teaches A non-transitory computer- readable medium storing instructions, the instructions comprising (See paragraph [0064] claim 33 of Koshimizu): controlling an impedance tuner coupled to a power source that outputs a RF signal to a load (See paragraphs [0058], [0059]); generating an impedance control signal to control an impedance match between the power source and the load (See [0065] [0066]); and generating the impedance control signal in response to a pulsed DC output signal from a second power source (See paragraph [0073]). Referring to the claim 24 Koshimizu teaches the non-transitory computer- readable medium storing instructions of claim 23, wherein the pulsed DC output signal has a plurality of half cycles, the instructions comprising: varying the impedance control signal in accordance with at least one of the plurality of half cycles. ( see Fig 1-3, paragraphs [0059]-[0071] and also [0136] and claims 1-4). Referring to the claim 25 Koshimizu teaches the non-transitory computer- readable medium of claim 23, the instructions comprising: varying at least one of a frequency of the RF signal or an actuator command to a matching network, wherein varying elements of a matching network, including at least one reactive element. ( see Fig 1-3, paragraphs [0059]-[0071] and also [0136] and claims 1-4). . Referring to the claim 26 Koshimizu teaches the non-transitory computer- readable medium of claim 23, wherein the pulsed DC output signal has a plurality of half cycles, including a negative half cycle and a positive half cycle, the instructions comprising: controlling an impedance over the negative half cycle and not controlling the impedance in over the positive half cycle. (See Paragraphs [0073] [0087], [0136]-[0138] and Fig 1-3). Referring to the claim 27 Koshimizu teaches the non-transitory computer-readable medium of claim 23, wherein the pulsed DC output signal has a plurality of half cycles, including a negative half cycle and a positive half cycle, the instructions comprising: controlling a first frequency of the RF signal during at least a portion of the negative half cycle. (See Fig 1-4C and 15A-D and paragraphs [0073], [0087] and [0172] teaches controlling RF signals) Referring to the claim 28 Koshimizu teaches the non-transitory computer-readable medium of claim 27, the instructions comprising: controlling a second frequency of the RF signal during at least a portion of the positive half cycle. (See Fig 1-4C and 15A- D and paragraphs [0073], [0087] and [0172] teaches controlling a second frequency). Referring to the claim 29 Koshimizu teaches the non-transitory computer- readable medium of claim 23, wherein the pulsed DC output signal has a plurality of half cycles (See Fig 1, 3-4C and 15 A-D) , the instructions comprising: determining the impedance control signal for a first of the plurality of half cycles (See Fig 3-4C and paragraph [0087]); and determining the impedance control signal for a second of the plurality of half cycles (See 15A-D where two or more states indicates the adjusting the impedance to load signal for a impedance match paragraph [0172] and claims 1-4). Conclusion Claims 1-29 are rejected The prior of art made of record and not relied upon is considered to pertinent to applicant’s disclosure. Applicants are directed to consider additional pertinent prior art included on the notice of references cited PTOL 892 attached here with. The examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicants. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim other passages and figures may apply. Applicant, in preparing the response should consider fully the entire reference as potentially teaching all or part of the claimed invention as well as the context of the passage as taught by the prior art or disclosed by the examiner. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SRINIVAS SATHIRAJU whose telephone number is (571)272-4250. The examiner can normally be reached 8:30AM-5.30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER H TANINGCO can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SRINIVAS . SATHIRAJU Primary Examiner Art Unit 2844
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Prosecution Timeline

Nov 29, 2023
Application Filed
Aug 06, 2025
Non-Final Rejection mailed — §102
Oct 23, 2025
Response Filed
Apr 08, 2026
Final Rejection mailed — §102
May 07, 2026
Response after Non-Final Action
May 12, 2026
Examiner Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+5.8%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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