Prosecution Insights
Last updated: May 29, 2026
Application No. 18/523,240

DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102
Filed
Nov 29, 2023
Priority
Feb 14, 2023 — RE 10-2023-0019319
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1026 granted / 1130 resolved
+22.8% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
1160
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
22.4%
-17.6% vs TC avg
§112
10.3%
-29.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1130 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, claims 1-17, in the reply filed on March 11, 2026 is acknowledged. Accordingly, claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 11, 2026. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on February 14, 2023. It is noted, however, that applicant has not filed a certified copy of the KR 10-2023-0019319 application as required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on November 29, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The information disclosure statement (IDS) submitted on July 18, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 9, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuwabara (US Pub 2005/0057151). In re claim 1, Kuwabara discloses a display panel (i.e. see at least Figures 17A-17C; paragraphs 0158-0177) comprising: a base layer (i.e. 1810); a pixel defining layer (i.e. 1811a, 1811b) which is disposed on the base layer and in which a light emitting opening is defined; a partition wall (i.e. 1810, 1812) which is disposed on the pixel defining layer and in which a partition wall opening corresponding to the light emitting opening is defined, the partition wall comprising: a first partition wall layer (i.e. 1800) disposed on the pixel defining layer and including a metal (i.e. see least paragraphs 0158-0169); and a second partition wall layer (i.e. 1812) disposed on the first partition wall layer and including at least one of amorphous carbon, polycrystalline silicon, or n-type silicon (i.e. in this case, polycrystalline silicon – see at least paragraph 0079); and a light emitting element comprising an anode (i.e. 1813), an intermediate layer (i.e. 1814), and a cathode (i.e. 1815) which is in contact with the partition wall (i.e. see at least paragraph 0158), the light emitting element being disposed in the partition wall opening (i.e. see at least Figures 17A-17B). In re claim 9, Kuwabara discloses wherein the first partition wall layer (i.e. 1800) is directly disposed on the pixel defining layer, and the second partition wall layer (i.e. 1812) is directly disposed on the first partition wall layer (i.e. see at least Figures 17A-17B showing at least part of 1812 is on 1800 on the side). In re claim 12, Kuwabara discloses wherein the cathode (i.e. 1815) is in contact (in this case, at least electrical or capacitively contact) with the second partition wall layer (i.e. 1812) (i.e. see at least Figures 17A-17B). Claims 2-8, 10, 11, and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 16 and 17 are allowed. The following is an examiner’s statement of reasons for allowance: The closest prior art of Kuwabara (US Pub 2005/0057151) either singularly or in combination fails to anticipate or render obvious a display panel comprising: a base layer; a pixel defining layer which is disposed on the base layer and in which a light emitting opening is defined; a partition wall which is disposed on the pixel defining layer and in which a partition wall opening corresponding to the light emitting opening is defined; and a light emitting element comprising an anode, an intermediate layer, and a cathode which is in contact with the partition wall, the light emitting element being disposed in the partition wall opening, wherein the partition wall comprises: a first partition wall layer disposed on the pixel defining layer and including a metal; a second partition wall layer disposed on the first partition wall layer and including a conductive inorganic material; and a third partition wall disposed on the second partition wall layer and including a metal or a silicon-based compound as recited in claim 16. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Nov 29, 2023
Application Filed
May 06, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641985
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 5m to grant Granted May 26, 2026
Patent 12637770
DEPOSITION DEVICE AND DEPOSITION METHOD
3y 4m to grant Granted May 26, 2026
Patent 12635405
QUANTUM DOT MATERIAL AND PREPARATION METHOD THEREFOR, QUANTUM DOT DISPLAY DEVICE, DISPLAY APPARATUS, METHOD FOR PATTERNING QUANTUM DOT FILM, AND METHOD FOR FABRICATING QUANTUM DOT LIGHT-EMITTING DEVICE
2y 11m to grant Granted May 19, 2026
Patent 12630761
ORGANIC ELECTROLUMINESCENCE ELEMENT AND ELECTRONIC DEVICE
1y 12m to grant Granted May 19, 2026
Patent 12628637
BACK END OF LINE INTERCONNECT STRUCTURE
2y 5m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1130 resolved cases by this examiner. Grant probability derived from career allowance rate.

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