Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 0373-0849PUS1
Filling Date: 11/29/23
Inventor: Ku et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-16 and 21-24 in the reply filed on 06/02/26 is acknowledged.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-5, 9, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2009/0115061 A1).
Regarding claim 1, Chen discloses an interconnection structure, comprising: a semiconductor substrate 20 (Fig. 12, Para. 20); an interlayer dielectric layer 24, 42 (Paras. 23, 32) that is disposed over the semiconductor substrate 20, and that is formed with an air gap 36 (Para. 27); and a first trench 56 (Para. 33) that is formed in the interlayer dielectric layer 24, 42, and that is disposed over the air gap 36.
Chen does not explicitly disclose the first metal trench. However, Chen discloses a trench is a metal 34 (Para. 32). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the conductive trench 56 is a metal for better electrical connection of the device (Fig. 12, common in the art).
Regarding claim 2, Chen discloses the interconnection structure according to claim 1, further comprising: a second metal trench 56 (right) that is formed in the interlayer dielectric layer 24, 42, and that is spaced apart from the first metal trench 56 (left) laterally; and a metal via 34 (Para. 32) that is formed in the interlayer dielectric layer 24, 34, and that extends from the second metal trench 56 to the semiconductor substrate 20; wherein the air gap 36 is spaced apart from the metal via 34 laterally.
Regarding claim 3, Chen discloses the interconnection structure according to claim 1, wherein the first metal trench 56 is formed in a top portion of the interlayer dielectric layer 24, 34, and the air gap 36 is formed in a bottom portion of the interlayer dielectric layer 24, 34.
Regarding claim 4, Chen discloses the interconnection structure according to claim 1, wherein the interlayer dielectric layer 24, 34 has a first portion 42 (Paras. 3, 32) which is porous and in which the first metal trench 56 is formed.
Regarding claim 5, Chen discloses the interconnection structure according to claim 4, wherein the interlayer dielectric layer 24, 42 has a second portion 24 which is different from the first portion in terms of material (Paras. 3, 32, 22, 23, material may be different) and in which the air gap 36 is formed.
Regarding claim 9, Chen discloses an interconnection structure (Fig. 12), comprising: a semiconductor substrate 20; an interlayer dielectric layer 24, 42 that is disposed over the semiconductor substrate 20, and that has a bottom portion formed with an air gap 36, a middle portion disposed over the bottom portion, and a top portion disposed over the middle portion (Fig. 12); and a first trench 56 (left) that is formed in the top portion of the interlayer dielectric layer 24, 34; wherein the middle portion 40 (Para. 31) of the interlayer dielectric layer separates the air gap 36 from the top portion of the interlayer dielectric layer 34.
Chen does not explicitly disclose a first metal trench. However, Chen discloses a trench is a metal 34 (Para. 32). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the conductive trench 56 is a metal for better electrical connection of the device (Fig. 12, common in the art).
Regarding claim 12, Chen discloses the interconnection structure according to claim 9, wherein the top portion 42 and the middle portion 38 (Para. 29) of the interlayer dielectric layer are porous (Paras. 3, 32, 23, 22).
Regarding claim 13, Chen discloses the interconnection structure according to claim 12, wherein the bottom portion of the interlayer dielectric layer 24 is different from the top portion of the interlayer dielectric layer 42 in terms of material (Paras. 3, 32, 22, 23, material may be different).
Allowable Subject Matter
5. Claims 6-8, 10-11, 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. Claims 21-23 and 24 are allowed.
7. The following is an examiner’s statement of reasons for allowance:
8. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method of fabricating a thin-film transistor (TFT) substrate, the method comprising: the first interlayer dielectric layer includes a first portion disposed between the first air gap and the first metal trench in combination with all other limitations as recited in claim 21.
9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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